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    • 1. 发明申请
    • High-resolution, patterned-media master mask
    • 高分辨率,图案化媒体主面具
    • US20090170010A1
    • 2009-07-02
    • US12006433
    • 2007-12-31
    • James G. BellesonMichael A. ParkerRobert O. Schwenker
    • James G. BellesonMichael A. ParkerRobert O. Schwenker
    • G03F1/00A61N5/00
    • H01J37/3174B82Y10/00B82Y40/00G03F7/0002G11B5/855Y10S430/143
    • A high-resolution, patterned-media master mask is disclosed. The high-resolution, patterned-media master mask includes an electron-absorption substrate for absorbing electrons from an electron beam (e-beam) during an e-beam exposure by an e-beam lithography process and suppressing a backscattering of the electrons based on an electron-backscattering-suppressing atomic number associated with a constituent atomic species of the electron-absorption substrate, wherein the electron-absorption substrate comprises a material composed of greater than fifty atomic percent of the constituent atomic species, and wherein the electron backscattering-suppressing atomic number is less than an atomic number eight. The high-resolution, patterned-media master mask further includes a patterned portion coupled with the electron-absorption substrate, wherein the patterned portion is patterned by the e-beam lithography process, and wherein a resolution of the patterned portion is increased in response to the electron-absorption substrate suppressing the backscattering of the electrons.
    • 公开了高分辨率图案化媒体主掩模。 高分辨率图案化媒体主掩模包括用于通过电子束光刻工艺在电子束曝光期间从电子束(电子束)吸收电子的电子吸收基板,并且基于以下原因抑制电子的反向散射 与电子吸收衬底的构成原子种类相关联的电子后向散射抑制原子序数,其中电子吸收衬底包括由组分原子种类大于50原子%组成的材料,并且其中电子后向散射抑制 原子数小于原子数8。 高分辨率图案化媒体主掩模还包括与电子吸收衬底耦合的图案部分,其中通过电子束光刻工艺对图案化部分进行构图,并且其中图案化部分的分辨率响应于 电子吸收衬底抑制电子的后向散射。
    • 3. 发明授权
    • Method for forming aluminum oxide dielectric isolation in integrated
circuits
    • 在集成电路中形成氧化铝介质隔离的方法
    • US4542579A
    • 1985-09-24
    • US592150
    • 1975-06-30
    • Michael R. PoponiakRobert O. Schwenker
    • Michael R. PoponiakRobert O. Schwenker
    • H01L21/76H01L21/316H01L21/762H01L21/20
    • H01L21/76227H01L21/31687Y10S148/085Y10S148/117
    • In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a semiconductor substrate comprising forming over the semiconductor substrate surface an electrically insulating layer of dielectric material having a plurality of openings therethrough and etching to form recesses in the semiconductor substrate exposed in the openings. Then, aluminum is deposited over the substrate so that an aluminum layer is formed on said layer of dielectric material as well as in said recesses. Next, the aluminum in the recesses is selectively anodized to form aluminum oxide, and the remaining aluminum on said layer of dielectric material is removed either by selectively etching away the aluminum layer or by a "lift-off" technique wherein the insulating layer of dielectric material under the aluminum is etched away thereby "lifting-off" and removing the aluminum.
    • 在集成电路的制造中,提供了一种用于在半导体衬底中形成介电隔离区域的方法,包括在半导体衬底表面上形成具有多个开口的介电材料的电绝缘层,并蚀刻以在半导体衬底中形成凹陷 在开口。 然后,在基板上沉积铝,使得在所述介电材料层以及所述凹部中形成铝层。 接下来,凹槽中的铝被选择性地阳极化以形成氧化铝,并且通过选择性地蚀刻掉铝层或通过“剥离”技术去除所述电介质材料层上的剩余的铝,其中电介质的绝缘层 铝下的材料被蚀刻掉,从而“脱落”并除去铝。
    • 5. 发明授权
    • Self-aligned micrometer bipolar transistor device and process
    • 自对准微米双极晶体管器件及工艺
    • US4303933A
    • 1981-12-01
    • US98588
    • 1979-11-29
    • Cheng T. HorngMichael R. PoponiakHans S. RupprechtRobert O. Schwenker
    • Cheng T. HorngMichael R. PoponiakHans S. RupprechtRobert O. Schwenker
    • H01L21/76H01L21/331H01L21/74H01L21/762H01L29/08H01L29/10H01L29/73H01L29/732H01L27/04H01L29/72
    • H01L21/743H01L21/76229H01L21/76232H01L29/0804H01L29/1004H01L29/7325Y10S148/131
    • A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.
    • 公开的器件制造方法是自对准工艺。 形成的装置具有小的垂直和水平尺寸。 器件区域被具有几乎垂直侧壁的深氧化物沟槽围绕。 深沟槽从外延硅表面通过N +子集电极区域延伸到P衬底中。 深沟的宽度约为2〜3.0亩。 从外延硅表面延伸到N +子集电极的上部的浅氧化物沟槽分离基极和集电极触点。 隔离区域和形成晶体管的硅的表面是共面的。 如图所示。 如图1所示,制造的双极晶体管具有台面型结构。 晶体管基极尺寸仅略大于发射极。 这种小的基极面积导致集电极电容低,这是超高性能集成电路器件中非常重要的参数。 所公开的结构中与晶体管基极的接触是通过围绕发射极的厚的重硼掺杂的多晶硅层实现的,并且与活性基底进行横向接触。
    • 10. 发明授权
    • Method for forming a non-epitaxial bipolar integrated circuit
    • 形成非外延双极性集成电路的方法
    • US4111720A
    • 1978-09-05
    • US783245
    • 1977-03-31
    • Alwin E. MichelRobert O. SchwenkerJames F. Ziegler
    • Alwin E. MichelRobert O. SchwenkerJames F. Ziegler
    • H01L27/08H01L21/265H01L21/331H01L21/74H01L21/76H01L29/36H01L29/73H01L21/26
    • H01L21/74H01L21/2652H01L29/36
    • A method for forming a non-epitaxial bipolar integrated circuit comprising first forming in a silicon substrate of one-type of conductivity, recessed silicon dioxide regions extending into the substrate and laterally enclosing at least one silicon substrate region of said one-type conductivity. Then, forming by ion implantation the first region of opposite-type conductivity which is fully enclosed laterally by said recessed silicon dioxide. This region is formed by directing a beam of ions of opposite-type conductivity impurity at said enclosed silicon region at such energy and dosage levels that the opposite conductivity-type impurity introduced into the substrate in said region will have a concentration peak at a point below the surface of this first region. Then, a region of said one-type conductivity is formed which extends from the surface into said first opposite-type conductivity region to a point between said concentration peak and said surface. Next, a second region of said opposite-type conductivity is formed which extends from the surface part way into said region of one-type conductivity.Preferably, the ion beam energy level is at least one MeV, and said concentration peak is at least one micron below the surface. It is further preferable that the energy and dosage levels of the beam of ions are selected so that the opposite-type conductivity impurity has a more gradual distribution gradient between the peak and the surface than between the peak and the junction of the first region with the substrate.