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1. 发明授权

US07543211B2 Toggle memory burst 有权
标题翻译：切换内存突发
公开(公告)号：US07543211B2
公开(公告)日：2009-06-02
申请号：US11047544
申请日：2005-01-31
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
IPC分类号： H03M13/00
CPC分类号： G11C7/22 , G11C11/16 , G11C2207/2263
摘要： A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.
摘要翻译：一种用于触发存储器的控制器，其通过读取触发存储器中的一组位来执行突发写入，并将该脉冲串的每个接收到的数据字与该组的一部分进行比较，以确定哪个单元切换以输入突发写入的数据切换存储器。在一个示例中，触发存储器包括具有使用多个自由磁性层的单元的磁阻随机存取存储器（MRAM），当沿两个方向受到一系列磁脉冲时，该状态在状态之间切换。因为对脉冲串的一组数据执行一次读取，所以执行突发写入所需的时间减少。

2. 发明授权

US06909631B2 MRAM and methods for reading the MRAM 有权
标题翻译： MRAM和读取MRAM的方法
公开(公告)号：US06909631B2
公开(公告)日：2005-06-21
申请号：US10679134
申请日：2003-10-02
申请人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
发明人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
IPC分类号： G11C11/15 , G11C11/16 , G11C11/14
CPC分类号： G11C11/16 , G11C11/15
摘要： An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.
摘要翻译：提供了一种MRAM，其通过利用每个存储单元中的隔离或选择装置来最小化MRAM密度的限制。另外，提供了用于读取MRAM的联动存储单元中的MTJ的方法。该方法包括确定至少部分地与MRAM的联动存储器单元的电阻相关联的电气值。切换联合存储器单元中的MTJ，并且在切换MTJ之后确定至少部分地与组合存储器单元的电阻相关联的第二电值。一旦确定了切换之前和切换之后的电气值，则分析两个电气值之间的差异，以确定MTJ的值。

3. 发明授权

US06744663B2 Circuit and method for reading a toggle memory cell 有权
公开(公告)号：US06744663B2
公开(公告)日：2004-06-01
申请号：US10184811
申请日：2002-06-28
申请人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (1300, 1500). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (1300, 1500). The first signal is compared to the second signal to determine the state of the MRAM cell.

4. 发明授权

US06693824B2 Circuit and method of writing a toggle memory 失效
标题翻译：写入切换存储器的电路和方法
公开(公告)号：US06693824B2
公开(公告)日：2004-02-17
申请号：US10186141
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.
摘要翻译：磁阻随机存取存储器以触发方式操作，使得其写入时其逻辑状态从其当前状态翻转到备用状态。这提供了更一致和可靠的编程，因为在切换操作期间的磁过渡能量状态是稳定的。然而，在写入情况下，这意味着在单元被翻转之前，单元格的状态必须被读取并与单元格的期望状态进行比较。如果单元已经处于所需的逻辑状态，则不应写入。写入前的读取时间损失通过在读取时开始写入处理而减少，然后在单元格已经处于所需状态时中止写入步骤。写入实际上可以在单元格上开始并被中止，而不会不利地影响单元的状态。

5. 发明授权

US06667899B1 Magnetic memory and method of bi-directional write current programming 失效
标题翻译：磁存储器和双向写入电流编程方法
公开(公告)号：US06667899B1
公开(公告)日：2003-12-23
申请号：US10401195
申请日：2003-03-27
申请人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A magnetic memory (400) is programmed by selectively conducting current in opposite directions in both word and bit lines to reduce electromigration effects in word lines and bit lines. Various criteria, such as a data value being programmed and a previous current direction are used to determine the direction of the write currents used in the word and bit lines during programming.
摘要翻译：通过在字线和位线中的相反方向选择性地导通电流来编程磁存储器（400），以减少字线和位线中的电迁移效应。使用诸如正在编程的数据值和先前的当前方向的各种标准来确定在编程期间在字和位线中使用的写入电流的方向。

6. 发明授权

US5614816A Low voltage reference circuit and method of operation 失效
标题翻译：低电压参考电路和操作方法
公开(公告)号：US5614816A
公开(公告)日：1997-03-25
申请号：US560876
申请日：1995-11-20
申请人： Joseph J. Nahas
发明人： Joseph J. Nahas
IPC分类号： G05F3/30 , G05F3/24 , H03F1/30 , G05F3/16
CPC分类号： G05F3/245 , Y10S323/907
摘要： A voltage reference generator circuit (600) that operates at low voltages may be obtained by using a summation circuit (618) to combine a divided bipolar junction voltage signal (616) and a multiplied voltage signal (622) that is proportional to absolute temperature. The voltage reference generator circuit (600) generates a voltage reference which is divided by a divide circuit (620) which produces the divided signal (616), and a voltage reference which is multiplied by a multiply circuit (630) which produces the multiplied signal (622). In another form, a bipolar junction voltage and a voltage that is proportional to absolute temperature may be converted to currents and summed to provide a current which is converted into the reference voltage output.
摘要翻译：可以通过使用求和电路（618）来组合分压双极结电压信号（616）和与绝对温度成正比的倍增电压信号（622）来获得在低电压下工作的电压参考发生器电路（600）。电压基准发生器电路（600）生成由产生分频信号（616）的除法电路（620）分压的电压基准，以及乘以产生相乘信号的乘法电路（630）的电压基准（622）。在另一种形式中，双极结电压和与绝对温度成比例的电压可以转换为电流并相加以提供转换为参考电压输出的电流。

7. 发明授权

US4625078A Fraud prevention in an electronic coin telephone set 失效
标题翻译：电子硬币电话机中的欺诈预防
公开(公告)号：US4625078A
公开(公告)日：1986-11-25
申请号：US567053
申请日：1983-12-30
申请人： Paul E. Crouch , Joseph J. Nahas , Howard Ng
发明人： Paul E. Crouch , Joseph J. Nahas , Howard Ng
IPC分类号： G07D5/08 , G07F1/04 , G07F5/22 , H04M17/02
CPC分类号： G07F1/04 , H04M17/023
摘要： This invention pertains to a microcomputer controlled coin telephone set which prevents coin call fraud and performs all of the coin discrimination functions. The microcomputer also checks the operational readiness of the telephone set to prevent the acceptance of coins into a hopper for late collection by a coin box unless or until the set is fully functional.
摘要翻译：本发明涉及一种防止硬币通话欺诈并执行所有硬币鉴别功能的微计算机控制硬币电话机。微型计算机还检查电话机的操作准备状况，以防止将硬币接收到料斗中以便由硬币盒进行晚期收集，除非或者直到该组件完全起作用。

8. 发明授权

US07154772B2 MRAM architecture with electrically isolated read and write circuitry 有权
标题翻译：具有电隔离读写电路的MRAM架构
公开(公告)号：US07154772B2
公开(公告)日：2006-12-26
申请号：US11076523
申请日：2005-03-09
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。类似地，写入电压不必降低以适应低电压型晶体管。整体存储器的大小保持有效小，同时提高性能。存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

9. 发明授权

US07082389B2 Method and apparatus for simulating a magnetoresistive random access memory (MRAM) 失效
标题翻译：用于模拟磁阻随机存取存储器（MRAM）的方法和装置
公开(公告)号：US07082389B2
公开(公告)日：2006-07-25
申请号：US10302203
申请日：2002-11-22
申请人： Joseph J. Nahas
发明人： Joseph J. Nahas
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and apparatus (500) for simulating a magnetoresistive random access memory (MRAM) (102) uses non-linear functions to model both non-linear magnetic tunnel junction (MTJ) effects and non-linear state switching effects. The method includes calculating a high threshold (THI) and a low threshold (TLO) based on a function of the hard axis current (IH). The easy axis current (IE) is compared to the high threshold (THI). If the easy axis current is greater than the high threshold, the MTJ resistance (RHI) is set to represent a stored high value. The easy axis current is compared to the low threshold. If the easy axis current is less than the low threshold, the MTJ resistance (RLO) is set to represent a stored low value. By using non-linear functions to model the MTJ effects and switching effects, the behavior of an MRAM (102) can be more accurately simulated.
摘要翻译：用于模拟磁阻随机存取存储器（MRAM）（102）的方法和装置（500）使用非线性函数来模拟非线性磁隧道结（MTJ）效应和非线性状态切换效应。该方法包括基于硬轴电流（I H H）的函数来计算高阈值（T HI）和低阈值（T LO） SUB>）。将易轴电流（I E E）与高阈值（T HI）进行比较。如果容易轴电流大于高阈值，则将MTJ电阻（R SUB HI）设置为表示存储的高值。将易轴电流与低阈值进行比较。如果容易轴电流小于低阈值，则将MTJ电阻（R LO LO）设置为表示存储的低值。通过使用非线性函数来建模MTJ效应和切换效果，可以更精确地模拟MRAM（102）的行为。

10. 发明授权

US06760266B2 Sense amplifier and method for performing a read operation in a MRAM 有权
公开(公告)号：US06760266B2
公开(公告)日：2004-07-06
申请号：US10185566
申请日：2002-06-28
申请人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/16 , G11C7/062 , G11C27/02
摘要： A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

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