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1. 发明授权

US06744663B2 Circuit and method for reading a toggle memory cell 有权
公开(公告)号：US06744663B2
公开(公告)日：2004-06-01
申请号：US10184811
申请日：2002-06-28
申请人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (1300, 1500). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (1300, 1500). The first signal is compared to the second signal to determine the state of the MRAM cell.

2. 发明授权

US06693824B2 Circuit and method of writing a toggle memory 失效
标题翻译：写入切换存储器的电路和方法
公开(公告)号：US06693824B2
公开(公告)日：2004-02-17
申请号：US10186141
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.
摘要翻译：磁阻随机存取存储器以触发方式操作，使得其写入时其逻辑状态从其当前状态翻转到备用状态。这提供了更一致和可靠的编程，因为在切换操作期间的磁过渡能量状态是稳定的。然而，在写入情况下，这意味着在单元被翻转之前，单元格的状态必须被读取并与单元格的期望状态进行比较。如果单元已经处于所需的逻辑状态，则不应写入。写入前的读取时间损失通过在读取时开始写入处理而减少，然后在单元格已经处于所需状态时中止写入步骤。写入实际上可以在单元格上开始并被中止，而不会不利地影响单元的状态。

3. 发明授权

US06711068B2 Balanced load memory and method of operation 有权
标题翻译：平衡负载记忆和操作方法
公开(公告)号：US06711068B2
公开(公告)日：2004-03-23
申请号：US10184720
申请日：2002-06-28
申请人： Chitra K. Subramanian , Brad J. Garni , Joseph J. Nahas , Halbert S. Lin , Thomas W. Andre
发明人： Chitra K. Subramanian , Brad J. Garni , Joseph J. Nahas , Halbert S. Lin , Thomas W. Andre
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/062 , G11C7/067 , G11C7/14 , G11C2207/005 , G11C2207/063
摘要： A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.
摘要翻译：存储器提供了一种感测方案，其保持数据到感测放大器的路由与参考或参考到读出放大器的路由之间的阻抗平衡。存储器的每个子阵列具有将数据耦合到也与子阵列相邻的数据线的相邻列解码器，并且可以被认为是列解码器的一部分。所选子阵列的数据通过其相邻数据线路由到读出放大器。作为所选子阵列的一部分的参考被耦合到未选择的子阵列的数据线。因此，在MRAM型存储器的情况下，参考优选地紧邻所选数据的位置，穿过相对于由数据采取的路由阻抗平衡的读出放大器的路线。

4. 发明授权

US07154772B2 MRAM architecture with electrically isolated read and write circuitry 有权
标题翻译：具有电隔离读写电路的MRAM架构
公开(公告)号：US07154772B2
公开(公告)日：2006-12-26
申请号：US11076523
申请日：2005-03-09
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。类似地，写入电压不必降低以适应低电压型晶体管。整体存储器的大小保持有效小，同时提高性能。存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

5. 发明授权

US06760266B2 Sense amplifier and method for performing a read operation in a MRAM 有权
公开(公告)号：US06760266B2
公开(公告)日：2004-07-06
申请号：US10185566
申请日：2002-06-28
申请人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/16 , G11C7/062 , G11C27/02
摘要： A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

6. 发明授权

US07543211B2 Toggle memory burst 有权
标题翻译：切换内存突发
公开(公告)号：US07543211B2
公开(公告)日：2009-06-02
申请号：US11047544
申请日：2005-01-31
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
IPC分类号： H03M13/00
CPC分类号： G11C7/22 , G11C11/16 , G11C2207/2263
摘要： A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.
摘要翻译：一种用于触发存储器的控制器，其通过读取触发存储器中的一组位来执行突发写入，并将该脉冲串的每个接收到的数据字与该组的一部分进行比较，以确定哪个单元切换以输入突发写入的数据切换存储器。在一个示例中，触发存储器包括具有使用多个自由磁性层的单元的磁阻随机存取存储器（MRAM），当沿两个方向受到一系列磁脉冲时，该状态在状态之间切换。因为对脉冲串的一组数据执行一次读取，所以执行突发写入所需的时间减少。

7. 发明授权

US06667899B1 Magnetic memory and method of bi-directional write current programming 失效
标题翻译：磁存储器和双向写入电流编程方法
公开(公告)号：US06667899B1
公开(公告)日：2003-12-23
申请号：US10401195
申请日：2003-03-27
申请人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A magnetic memory (400) is programmed by selectively conducting current in opposite directions in both word and bit lines to reduce electromigration effects in word lines and bit lines. Various criteria, such as a data value being programmed and a previous current direction are used to determine the direction of the write currents used in the word and bit lines during programming.
摘要翻译：通过在字线和位线中的相反方向选择性地导通电流来编程磁存储器（400），以减少字线和位线中的电迁移效应。使用诸如正在编程的数据值和先前的当前方向的各种标准来确定在编程期间在字和位线中使用的写入电流的方向。

8. 发明授权

US06711052B2 Memory having a precharge circuit and method therefor 有权
标题翻译：具有预充电电路的存储器及其方法
公开(公告)号：US06711052B2
公开(公告)日：2004-03-23
申请号：US10185488
申请日：2002-06-28
申请人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C700
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。每个具有多个串联级的可切换电流镜接收公共参考电流。定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。位线在公共端连接在一起，字线在公共端连接在一起。通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。位线组可以通过金属选项来连接，以调整编程电流的转换时间。

9. 发明授权

US06657889B1 Memory having write current ramp rate control 有权
标题翻译：具有写入电流斜坡率控制的存储器
公开(公告)号：US06657889B1
公开(公告)日：2003-12-02
申请号：US10185075
申请日：2002-06-28
申请人： Chitra K. Subramanian , Thomas W. Andre , Bradley J. Garni , Halbert S. Lin , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Bradley J. Garni , Halbert S. Lin , Joseph J. Nahas
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。每个具有多个串联级的可切换电流镜接收公共参考电流。定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。位线在公共端连接在一起，字线在公共端连接在一起。通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。位线组可以通过金属选项来连接，以调整编程电流的转换时间。

10. 发明授权

US06859388B1 Circuit for write field disturbance cancellation in an MRAM and method of operation 失效
标题翻译： MRAM中的磁场干扰消除电路及其操作方法
公开(公告)号：US06859388B1
公开(公告)日：2005-02-22
申请号：US10656646
申请日：2003-09-05
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
IPC分类号： G11C11/14 , G11C11/00
CPC分类号： G11C11/14
摘要： A circuit and method for counteracting stray magnetic fields generated by write currents in an MRAM memory reuses the write current in adjoining write columns via a current redistribution bus at a first end of the write lines. A first switch connected to a second end of each write line controls the write current in the write line. If the first switch is not conductive, a second switch connects the second end of the write line to a reference voltage terminal. For write lines located at sub-array edges, a predetermined amount of spacing may be used to avoid magnetic field disturbance in an adjacent sub-array. The number of spaces required can be minimized by specific activation of write line switches.
摘要翻译：用于抵消由MRAM存储器中的写入电流产生的杂散磁场的电路和方法在写入线的第一端通过电流再分配总线重新使用相邻写入列中的写入电流。连接到每条写入线的第二端的第一开关控制写入线中的写入电流。如果第一开关不导通，则第二开关将写入线的第二端连接到参考电压端子。对于位于子阵列边缘的写入线，可以使用预定量的间隔来避免相邻子阵列中的磁场干扰。可以通过写入线开关的特定激活来最小化所需的空间数量。

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