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1. 发明申请

US20080057629A1 Integrated circuit cooling and insulating device and method 失效
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US20080057629A1
公开(公告)日：2008-03-06
申请号：US11977524
申请日：2007-10-25
申请人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
发明人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

2. 发明申请

US20080048314A1 Integrated circuit cooling and insulating device and method 失效
公开(公告)号：US20080048314A1
公开(公告)日：2008-02-28
申请号：US11977515
申请日：2007-10-25
申请人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
发明人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

3. 发明申请

US20060249837A1 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US20060249837A1
公开(公告)日：2006-11-09
申请号：US11482308
申请日：2006-07-07
申请人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
发明人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

4. 发明申请

US20060046322A1 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US20060046322A1
公开(公告)日：2006-03-02
申请号：US10930252
申请日：2004-08-31
申请人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
发明人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

5. 发明申请

US20050029501A1 Low k interconnect dielectric using surface transformation 有权
标题翻译：低k互连电介质使用表面变换
公开(公告)号：US20050029501A1
公开(公告)日：2005-02-10
申请号：US10931593
申请日：2004-08-31
申请人： Joseph Geusic , Paul Farrar , Arup Bhattacharyya
发明人： Joseph Geusic , Paul Farrar , Arup Bhattacharyya
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/532 , H01L21/76
CPC分类号： H01L21/0212 , H01L21/02145 , H01L21/02161 , H01L21/02203 , H01L21/02266 , H01L21/02354 , H01L21/31058 , H01L21/31138 , H01L21/3122 , H01L21/31695 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.
摘要翻译：提供系统，器件和方法，以通过提供低k绝缘体来提高集成电路的性能。一个方面是集成电路绝缘体结构。一个实施例包括绝缘体材料的固体结构，以及形成在固体结构内的至少一个空隙的精确确定的布置，其降低绝缘体结构的有效介电常数。一个方面是形成低k绝缘体结构的方法。在一个实施例中，沉积绝缘体材料，并且在绝缘体材料的表面中形成至少一个孔的预定布置。绝缘体材料被退火，使得低k电介质材料进行表面变换，以将至少一个孔的布置转换成绝缘体材料表面下方的至少一个空白空间的预定布置。本文提供了其他方面。

6. 发明申请

US20050023638A1 Scalable high performance antifuse structure and process 有权
标题翻译：可扩展的高性能反熔丝结构和工艺
公开(公告)号：US20050023638A1
公开(公告)日：2005-02-03
申请号：US10931601
申请日：2004-08-31
申请人： Arup Bhattacharyya , Joseph Geusic
发明人： Arup Bhattacharyya , Joseph Geusic
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.
摘要翻译：为可扩展的高性能反熔丝结构和工艺提供了系统和方法，该结构和工艺具有低RC分量，均匀的介质击穿和非常低的有效介电常数（keff），使得编程脉冲电压可以用Vdd进行扩展。本主题的一个方面是反熔丝装置，其被定位或耦合在第一金属层和第二金属层之间。反熔丝装置的一个实施例包括多孔反熔丝电介质层和与多孔反熔丝电介质层接触的至少一个注入硅富集绝缘体（SRI）层。在一个实施例中，多孔反熔丝电介质层包括形成有空气填充空隙的SiO 2。在一个实施例中，至少一个喷射器SRI层包括夹着多孔反熔丝电介质层的两个注入器富硅氮化物层。本文提供了其他方面。

7. 发明申请

US20050020094A1 Strained semiconductor by full wafer bonding 有权
标题翻译：应变半导体通过全晶圆键合
公开(公告)号：US20050020094A1
公开(公告)日：2005-01-27
申请号：US10623788
申请日：2003-07-21
申请人： Leonard Forbes , Joseph Geusic , Salman Akram
发明人： Leonard Forbes , Joseph Geusic , Salman Akram
IPC分类号： H01L21/469 , H01L21/762
CPC分类号： H01L21/76254
摘要： One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.
摘要翻译：本公开的一个方面涉及一种用应变半导体形成晶片的方法。在该方法的各种实施例中，在半导体膜和衬底晶片之一上形成预定轮廓。将半导体膜结合到基板晶片上，并且将预定轮廓拉直以在半导体膜中引起预定应变。在各种实施例中，衬底晶片弯曲到弯曲位置，当衬底晶片处于弯曲位置时，衬底晶片的一部分结合到半导体层，并且衬底晶片被松弛以在半导体中引起预定应变层。本文提供了其它方面和实施例。

8. 发明申请

US20050282385A1 Conductive material patterning methods 有权
公开(公告)号：US20050282385A1
公开(公告)日：2005-12-22
申请号：US11215465
申请日：2005-08-30
申请人： Joseph Geusic , Alan Reinberg
发明人： Joseph Geusic , Alan Reinberg
IPC分类号： H01L21/321 , H01L21/3213 , H01L21/44 , H01L21/768 , H05K3/02 , H05K3/10
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/321 , H01L21/32135 , H01L21/76823 , H01L21/76825 , H01L21/76838 , H01L21/76841 , H01L21/76856 , H01L21/76873 , H01L21/76874 , H01L21/76885 , H01L21/76888 , H05K3/02 , H05K3/105 , H05K3/108 , H05K2201/0175 , H05K2203/0315 , H05K2203/1142 , H05K2203/1157
摘要： A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

9. 发明申请

US20050236954A1 Microcavity discharge device 失效
标题翻译：微腔放电装置
公开(公告)号：US20050236954A1
公开(公告)日：2005-10-27
申请号：US11150350
申请日：2005-06-13
申请人： Joseph Geusic
发明人： Joseph Geusic
IPC分类号： G03F7/20 , H01J1/00 , H01J9/18 , H01J61/09 , H01J61/30 , H05G2/00
CPC分类号： H05G2/003 , B82Y10/00 , G03F7/70016 , G03F7/70033 , H01J9/18 , H01J61/09 , H01J61/30
摘要： A microcavity discharge device generates radiation with wavelengths in the range of from 11 to 14 nanometers. The device has a semiconductor plug, a dielectric layer, and an anode layer. A microcavity extends completely through the anode and dielectric layers and partially into the semiconductor plug. According to one aspect of the invention, a substrate layer has an aperture aligned with the microcavity. The microcavity is filled with a discharge gas under pressure which is excited by a combination of constant DC current and a pulsed current to produce radiation of the desired wavelength. The radiation is emitted through the base of the microcavity. A second embodiment has a metal layer which transmits radiation with wavelengths in the range of from 11 to 12 nanometers, and which excludes longer wavelengths from the emitted beam.
摘要翻译：微腔放电装置产生波长在11至14纳米范围内的辐射。该器件具有半导体插头，电介质层和阳极层。微腔完全延伸穿过阳极和电介质层，并部分地延伸到半导体插头中。根据本发明的一个方面，基底层具有与微腔对准的孔。微腔内填充有压力下的放电气体，该放电气体通过恒定直流电流和脉冲电流的组合激发，以产生所需波长的辐射。辐射通过微腔的底部发射。第二实施例具有传输波长在11至12纳米范围内的辐射的金属层，并且其不包括来自发射光束的较长波长。

10. 发明申请

US20050026360A1 Method and structure for high capacitance memory cells 有权
公开(公告)号：US20050026360A1
公开(公告)日：2005-02-03
申请号：US10929253
申请日：2004-08-30
申请人： Joseph Geusic , Leonard Forbes , Kie Ahn
发明人： Joseph Geusic , Leonard Forbes , Kie Ahn
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/1087 , Y10S977/888 , Y10S977/943
摘要： A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.

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