专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4013751A Fibrils and processes for the manufacture thereof 失效
标题翻译：其制造方法及其制造方法
公开(公告)号：US4013751A
公开(公告)日：1977-03-22
申请号：US479357
申请日：1974-06-14
申请人： Joseph C. Davis , Francis R. Galiano , Robert W. Hill
发明人： Joseph C. Davis , Francis R. Galiano , Robert W. Hill
IPC分类号： B01J2/06 , D01D5/11 , D01D5/40
CPC分类号： D01D5/11 , D01D5/40 , D21H13/14 , D21H5/202
摘要： A process for producing a mass of entangled solvent swollen polymer filaments which can be converted into paper-making fibrils by subsequent refining. An olefin polymer such as polyethylene having an inherent viscosity of at least 3.5 is dissolved in a hot solvent. The hot polymer solution is subjected to timed sequential steps in which the polymer solution first is sheared and attenuated into fine polymer streams. The hot polymer streams then are cooled to precipitate the polymer which is recovered as a mass of entangled solvent swollen filaments. These filaments can be beaten in a non-solvent liquid such as isopropanol to prepare fibrils having diameters on the order of about 5 to 30 microns and lengths of about 1 to 15 millimeters.

2. 发明授权

US06381564B1 Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators 有权
标题翻译：使用响应面方法确定复杂模拟器的最佳调谐参数的方法和系统
公开(公告)号：US06381564B1
公开(公告)日：2002-04-30
申请号：US09304189
申请日：1999-05-03
申请人： Joseph C. Davis , Karthik Vasanth , Sharad Saxena , Purnendu K. Mozumder , Suraj Rao , Chenjing L. Fernando , Richard G. Burch
发明人： Joseph C. Davis , Karthik Vasanth , Sharad Saxena , Purnendu K. Mozumder , Suraj Rao , Chenjing L. Fernando , Richard G. Burch
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation. The objective function is, for example, the square root of the sum of the squares at all of the differences between the target values and the observed values at all points being investigated. The optimizing in the optimizer is preferably a gain function which adjusts the parameters to the input based upon the error signal to minimize the error signal.
摘要翻译：一种用于为复杂模拟器提供最佳调谐的方法和系统。该方法和系统包括最初构建至少一个具有输入和输出端的RSM模型。然后，通过从至少一个RSM模型的输出端子和实验数据的输出构造目标函数来提供无模拟优化功能。目标函数在优化器中进行优化，优化的目标函数馈送到RSM的输入端。建立至少一个RSM模型，包括建立模拟范围，运行设计实验的仿真实验，从所提取的实验中提取相关数据，并从提取的相关数据构建RSM模型。运行模拟实验的步骤包括运行DOE / Opt操作的步骤。目标函数例如是目标值与被调查的所有点的观测值之间的所有差异的平方和的平方根。优化器中的优化优选地是基于误差信号调整输入参数的增益函数，以最小化误差信号。

3. 发明授权

US07673262B2 System and method for product yield prediction 失效
标题翻译：产品产量预测的系统和方法
公开(公告)号：US07673262B2
公开(公告)日：2010-03-02
申请号：US12119862
申请日：2008-05-13
申请人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
发明人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G05B15/02 , H01L22/20 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.
摘要翻译：用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。提取引擎从提出的产品布局中提取预定的布局属性。在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

4. 发明授权

US07356800B2 System and method for product yield prediction 有权
公开(公告)号：US07356800B2
公开(公告)日：2008-04-08
申请号：US11503323
申请日：2006-08-10
申请人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
发明人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G05B15/02 , H01L22/20 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

5. 发明授权

US06388288B1 Integrating dual supply voltages using a single extra mask level 有权
标题翻译：使用单个额外的掩模级别集成双电源电压
公开(公告)号：US06388288B1
公开(公告)日：2002-05-14
申请号：US09276783
申请日：1999-03-25
申请人： Karthik Vasanth , Sharad Saxena , Richard G. Burch , Purnendu K. Mozumder , Joseph C. Davis , Chenjing L. Fernando , Suraj Rao
发明人： Karthik Vasanth , Sharad Saxena , Richard G. Burch , Purnendu K. Mozumder , Joseph C. Davis , Chenjing L. Fernando , Suraj Rao
IPC分类号： H01L2976
CPC分类号： H01L21/823418
摘要： Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.
摘要翻译：通过仅对周围晶体管的MDD注入进行优化，可以通过最小额外的掩模来实现双电压集成在一起，而对于两种晶体管类型，其他植入物保持相同。这符合生命周期规格，无需费用。

6. 发明申请

US20080282210A1 System And Method For Product Yield Prediction 失效
标题翻译：产品产量预测的系统和方法
公开(公告)号：US20080282210A1
公开(公告)日：2008-11-13
申请号：US12119862
申请日：2008-05-13
申请人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
发明人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G05B15/02 , H01L22/20 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.
摘要翻译：用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。提取引擎从提出的产品布局中提取预定的布局属性。在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

7. 发明授权

US07434197B1 Method for improving mask layout and fabrication 有权
标题翻译：改进掩模布局和制造的方法
公开(公告)号：US07434197B1
公开(公告)日：2008-10-07
申请号：US11262148
申请日：2005-10-28
申请人： Christoph Dolainsky , Jonathan O. Burrows , Dennis Ciplickas , Joseph C. Davis , Rakesh Vallishayee , Howard Read , Larg. H. Weiland , Christopher Hess
发明人： Christoph Dolainsky , Jonathan O. Burrows , Dennis Ciplickas , Joseph C. Davis , Rakesh Vallishayee , Howard Read , Larg. H. Weiland , Christopher Hess
IPC分类号： G06F17/50
CPC分类号： G03F7/705
摘要： A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.
摘要翻译：在面罩布局设计中识别出热点。热点表示具有容易产生一个或多个制造缺陷的一个或多个特征几何形状的面罩布局设计的局部区域。为识别的热点产生测试结构。测试结构被定义为模拟易于产生一个或多个制造缺陷的一个或多个特征几何形状。使用特定的制造工艺在测试晶片上制造测试结构。检查制造的测试结构以识别对于掩模布局设计或指定制造工艺的热点的特征几何形状的一个或多个调整，其中所识别的调整能够减少制造缺陷。

8. 发明授权

US06311096B1 Design of microelectronic process flows for manufacturability and performance 有权
标题翻译：微电子工艺流程的可制造性和性能设计
公开(公告)号：US06311096B1
公开(公告)日：2001-10-30
申请号：US09283479
申请日：1999-04-01
申请人： Sharad Saxena , Karthik Vasanth , Richard G. Burch , Purnendu K. Mozumder , Suraj Rao , Joseph C. Davis
发明人： Sharad Saxena , Karthik Vasanth , Richard G. Burch , Purnendu K. Mozumder , Suraj Rao , Joseph C. Davis
IPC分类号： G06F1900
CPC分类号： G06Q10/06
摘要： A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.
摘要翻译：提供统计设计方法，用于通过统计设计来最小化制造差异对半导体制造的影响，其旨在减少变异性对器件行为的影响。该方法基于处理流程的马尔科夫表示，其捕获半导体制造的顺序和随机性质，并且能够分离设备和过程模型，将过程模块从可观察的晶片状态进行统计建模以及用于大型设计空间的统计优化的近似。该方法的统计估计分量导致了对所有制造流量的晶体管性能的可变性的非常准确的预测。统计优化可以实现所有晶体管性能和可靠性目标的器件，并减少关键晶体管性能的变化。

9. 发明授权

US6157062A Integrating dual supply voltage by removing the drain extender implant from the high voltage device 有权
标题翻译：通过从高压设备中移除漏极延长器植入物来整合双电源电压
公开(公告)号：US6157062A
公开(公告)日：2000-12-05
申请号：US287227
申请日：1999-04-06
申请人： Karthik Vasanth , Richard G. Burch , Sharad Saxena , Purnendu K. Mozumder , Chenjing L. Fernando , Joseph C. Davis , Suraj Rao
发明人： Karthik Vasanth , Richard G. Burch , Sharad Saxena , Purnendu K. Mozumder , Chenjing L. Fernando , Joseph C. Davis , Suraj Rao
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L29/76
CPC分类号： H01L21/823418 , H01L21/8238
摘要： A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.
摘要翻译：通过调整栅极侧壁间隔物厚度和源极/漏极注入，在高电压晶体管中制造双电压芯片，其中没有中间掺杂（LDD或MDD）区域。

10. 发明授权

US07373625B2 System and method for product yield prediction 有权
标题翻译：产品产量预测的系统和方法
公开(公告)号：US07373625B2
公开(公告)日：2008-05-13
申请号：US11503433
申请日：2006-08-10
申请人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
发明人： Brian E. Stine , Christopher Hess , John Kibarian , Kimon Michaels , Joseph C. Davis , Purnendu K. Mozumder , Sherry F. Lee , Larg H. Weiland , Dennis J. Ciplickas , David M. Stashower
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G05B15/02 , H01L22/20 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.
摘要翻译：用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。提取引擎从提出的产品布局中提取预定的布局属性。在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式