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1. 发明授权

US07434197B1 Method for improving mask layout and fabrication 有权
标题翻译：改进掩模布局和制造的方法
公开(公告)号：US07434197B1
公开(公告)日：2008-10-07
申请号：US11262148
申请日：2005-10-28
申请人： Christoph Dolainsky , Jonathan O. Burrows , Dennis Ciplickas , Joseph C. Davis , Rakesh Vallishayee , Howard Read , Larg. H. Weiland , Christopher Hess
发明人： Christoph Dolainsky , Jonathan O. Burrows , Dennis Ciplickas , Joseph C. Davis , Rakesh Vallishayee , Howard Read , Larg. H. Weiland , Christopher Hess
IPC分类号： G06F17/50
CPC分类号： G03F7/705
摘要： A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.
摘要翻译：在面罩布局设计中识别出热点。热点表示具有容易产生一个或多个制造缺陷的一个或多个特征几何形状的面罩布局设计的局部区域。为识别的热点产生测试结构。测试结构被定义为模拟易于产生一个或多个制造缺陷的一个或多个特征几何形状。使用特定的制造工艺在测试晶片上制造测试结构。检查制造的测试结构以识别对于掩模布局设计或指定制造工艺的热点的特征几何形状的一个或多个调整，其中所识别的调整能够减少制造缺陷。

2. 发明授权

US07644388B1 Method for reducing layout printability effects on semiconductor device performance 有权
标题翻译：降低布局印刷性对半导体器件性能的影响的方法
公开(公告)号：US07644388B1
公开(公告)日：2010-01-05
申请号：US11540453
申请日：2006-09-29
申请人： Lidia Daldoss , Sharad Saxena , Christoph Dolainsky , Rakesh R. Vallishayee
发明人： Lidia Daldoss , Sharad Saxena , Christoph Dolainsky , Rakesh R. Vallishayee
IPC分类号： G06F17/50
CPC分类号： H01L22/34 , G03F1/36
摘要： A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure representative of the identified layout configuration is obtained. A design of experiment is associated with the test structure. The design of experiment is defined to investigating effects of variations of one or more layout attributes in the test structure. Multiple instance of the test structure are fabricated on a wafer according to the design of experiment. Electrical performance characteristics of the fabricated test structures are measured. Based on the measured electrical performance characteristics, one or more layout attributes of the test structure capable of causing functional or parametric failure are determined.
摘要翻译：在一系列光刻工艺条件下对掩模布局进行可印刷性模拟。在掩模布局中识别能够引起半导体器件中的功能或参数故障的布局配置。获得表示所识别的布局配置的测试结构。实验设计与测试结构相关。实验设计被定义为调查测试结构中一个或多个布局属性的变化的影响。根据实验设计，在晶片上制造测试结构的多个实例。测量制造的测试结构的电气性能特征。基于测量的电气性能特征，确定能够引起功能或参数故障的测试结构的一个或多个布局属性。

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