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1. 发明授权

US5976944A Integrated circuit with thin film resistors and a method for co-patterning thin film resistors with different compositions 失效
标题翻译：具有薄膜电阻的集成电路和用于对具有不同组成的薄膜电阻器进行协同图案化的方法
公开(公告)号：US5976944A
公开(公告)日：1999-11-02
申请号：US799793
申请日：1997-02-12
申请人： Joseph Andre Czagas , George Bajor , Leonel Ernesto Enriquez
发明人： Joseph Andre Czagas , George Bajor , Leonel Ernesto Enriquez
IPC分类号： H01C17/08 , H01L21/02 , H01L21/822 , H01L27/01 , H01L27/04 , H01L21/20
CPC分类号： H01L28/24 , H01L27/016
摘要： FIG. 5b shows a first thin film resistor 14 formed by direct etching or lift off on a first dielectric layer 12 that covers an integrated circuit (not shown) in a silicon substrate 10. A patterned layer of photoresist covers a portion of the second thin film resistor material 30. The second thin film resistor material 30 is different from the first thin film resistor material 14. The exposed portion of the second thin film resistor material 30 is removed to leave first and second thin film resistors on the first dielectric layer 12.
摘要翻译：图。图5b示出了通过在覆盖硅衬底10中的集成电路（未示出）的第一电介质层12上直接蚀刻或剥离而形成的第一薄膜电阻器14.图案化的光致抗蚀剂层覆盖了第二薄膜电阻器的一部分材料30.第二薄膜电阻器材料30与第一薄膜电阻器材料14不同。去除第二薄膜电阻器材料30的暴露部分以在第一介电层12上留下第一和第二薄膜电阻器。

2. 发明授权

US06365953B2 Wafer trench article and process 有权
标题翻译：晶圆沟的文章和过程
公开(公告)号：US06365953B2
公开(公告)日：2002-04-02
申请号：US09283530
申请日：1999-04-01
申请人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
发明人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
IPC分类号： H01L2900
CPC分类号： H01L21/7624 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286
摘要： A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.
摘要翻译：键合晶片100具有具有限定器件区域18的隔离沟槽30的器件衬底16.在填充沟槽30之前去除氧化物骨骼结构。沟槽中的空隙36与沟槽的顶部间隔开。沟槽被氧化物层30覆盖并填充有多晶硅34.包括CVD衬垫氧化物层和氮化硅50的LOCOS掩模结构覆盖沟槽和相邻的器件衬底区域。

3. 发明授权

US5744852A Bonded wafer 失效
标题翻译：粘合晶片
公开(公告)号：US5744852A
公开(公告)日：1998-04-28
申请号：US710694
申请日：1996-09-19
申请人： Jack H. Linn , George Bajor , George V. Rouse
发明人： Jack H. Linn , George Bajor , George V. Rouse
IPC分类号： H01L21/20 , H01L29/06
CPC分类号： H01L21/2007 , Y10S148/012 , Y10S438/974
摘要： A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.
摘要翻译：具有键合结的键合晶片由于在键合结处的氧化物水平低而具有低电阻率。从晶片去除原生氧化物层的等离子体暴露于晶片。等离子体在晶片上形成疏水聚合物密封，在暴露于空气中时抑制随后的天然氧化物生长。将要接合的晶片上的聚合物密封件压在一起，并且将晶片退火以在非氧化环境中形成接合晶片。所形成的键合键主要是硅与硅和硅与碳键。

4. 发明授权

US5395774A Methods for forming a transistor having an emitter with enhanced efficiency 失效
标题翻译：用于形成具有提高效率的发射极的晶体管的方法
公开(公告)号：US5395774A
公开(公告)日：1995-03-07
申请号：US123157
申请日：1993-09-07
申请人： George Bajor , Anthony L. Rivoli , Jack H. Linn
发明人： George Bajor , Anthony L. Rivoli , Jack H. Linn
IPC分类号： H01L29/73 , H01L21/225 , H01L21/314 , H01L21/331 , H01L29/165 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L21/314 , H01L29/165 , H01L29/7375
摘要： Methods of forming a carbon containing, minority carrier barrier layer on the surface of a semiconductor, which methods may be used to form barriers between the emitter of a single crystal transistor and a polysilicon layer in electrical contact therewith, and thus transistors with an emitter with enhanced efficiency.
摘要翻译：在半导体表面上形成含碳少数载流子阻挡层的方法，可以使用这些方法在单晶晶体管的发射极和与其接触的多晶硅层之间形成屏障，从而形成具有发射极提高效率。

5. 发明授权

US5504033A Method for forming recessed oxide isolation containing deep and shallow trenches 失效
标题翻译：用于形成包含深和浅沟槽的凹陷氧化物隔离的方法
公开(公告)号：US5504033A
公开(公告)日：1996-04-02
申请号：US339966
申请日：1994-11-15
申请人： George Bajor , Anthony L. Rivoli
发明人： George Bajor , Anthony L. Rivoli
IPC分类号： H01L21/762 , H01L21/763 , H01L21/302
CPC分类号： H01L21/76224 , H01L21/76264 , H01L21/763 , H01L21/76275 , H01L21/76283
摘要： Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.
摘要翻译：嵌入的隔离氧化物沉积在浅沟槽中，同时在深隔离沟槽中沉积氧化物。两个沟槽填充物的单一平面化提供了有效的凹陷隔离氧化物，而没有鸟嘴或LOCOS隔离氧化物的鸟头问题。通过氧化物和多晶硅的连续共形沉积的自对准沟槽填充，随后进行平面化以从沟槽移除多晶硅。剩余的多晶硅可以用作氧化物蚀刻掩模以除去除了沟槽中的所有氧化物。

6. 发明授权

US4771016A Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor 失效
标题翻译：使用快速热处理制造晶圆粘合的半导体
公开(公告)号：US4771016A
公开(公告)日：1988-09-13
申请号：US42135
申请日：1987-04-24
申请人： George Bajor , Joseph S. Raby
发明人： George Bajor , Joseph S. Raby
IPC分类号： H01L21/20 , H01L21/762 , H01L21/76
CPC分类号： H01L21/2007 , H01L21/76251 , Y10S148/012 , Y10S148/135 , Y10S148/15
摘要： A method of forming a high quality silicon on insulator semiconductor device using wafer bonding. The annealing time for the wafer bonding process is substantially reduced through the use of a rapid thermal annealer, thereby resulting in minimizing the redistribution of the doping concentration resulting from the annealing process.
摘要翻译：使用晶片接合形成高质量硅绝缘体上半导体器件的方法。通过使用快速热退火炉，晶片接合工艺的退火时间显着降低，从而导致由退火过程产生的掺杂浓度的再分配最小化。

7. 发明授权

US06812108B2 BICMOS process with low temperature coefficient resistor (TCRL) 失效
标题翻译： BICMOS工艺采用低温系数电阻（TCRL）
公开(公告)号：US06812108B2
公开(公告)日：2004-11-02
申请号：US10393181
申请日：2003-03-19
申请人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George Bajor
发明人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George Bajor
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/763 , H01L21/8249 , H01L27/0635
摘要： A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.
摘要翻译：低温度系数电阻（TCRL）具有一些未修复的离子注入损伤。损坏部分会提高电阻，使电阻对工作温度波动较不敏感。多晶硅薄膜低温系数电阻器和电阻器制造方法克服了现有技术的电阻系数问题，同时消除了BiCMOS制造工艺的步骤，优化了双极设计的权衡，改善了无源器件隔离。在绝缘层（通常为二氧化硅或氮化硅）上形成电阻电阻器（TCRL）的低温度系数，该层包含具有相对高浓度的一种或多种物质的掺杂剂的多晶硅。对于注入电阻器而言，使用退火工艺，其比典型的现有技术的注入电阻器的退火工艺短，从而在电阻器中留下一些有意的未退火损坏。计划的损坏使TCRL具有更高的阻力，而不增加其温度系数。使用制造电阻器的方法，其组合分开的间隔氧化物沉积，提供具有不同扩散系数的掩埋层，并入双重介质沟槽侧壁作为抛光停止点，提供精确控制发射极基底尺寸的间隔结构，以及将双极和CMOS器件集成到任何一种类型的特性上都可忽略不计。

8. 发明授权

US06551897B2 Wafer trench article and process 有权
公开(公告)号：US06551897B2
公开(公告)日：2003-04-22
申请号：US09993968
申请日：2001-11-16
申请人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
发明人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
IPC分类号： H01L21762
CPC分类号： H01L21/7624 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286
摘要： A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

9. 发明授权

US5807780A High frequency analog transistors method of fabrication and circuit implementation 失效
标题翻译：高频模拟晶体管的制造和电路实现方法
公开(公告)号：US5807780A
公开(公告)日：1998-09-15
申请号：US462851
申请日：1995-06-05
申请人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
发明人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/8228 , H01L21/84 , H01L27/06 , H01L27/082 , H01L27/12 , H01L29/08 , H01L29/167 , H01L29/732 , H01L29/808 , H01L29/8605 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/8228 , H01L21/82285 , H01L21/84 , H01L27/0623 , H01L27/082 , H01L27/0826 , H01L27/1203 , H01L29/0821 , H01L29/167 , H01L29/7325 , H01L29/808 , H01L29/8605
摘要： A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.
摘要翻译：用于介质隔离的高频互补模拟双极和CMOS晶体管的制造工艺。多晶硅非本征基极，具有在内部基底形成之后形成的侧壁间隔物的多晶硅发射体提供高电流增益，大的发射极到基极击穿电压，大的早期电压和高截止频率。

10. 发明授权

US06441447B1 Co-patterning thin-film resistors of different compositions with a conductive hard mask and method for same 失效
标题翻译：使用导电硬掩模对不同组成的薄膜电阻器进行共同构图及其方法
公开(公告)号：US06441447B1
公开(公告)日：2002-08-27
申请号：US09367325
申请日：1999-08-11
申请人： Joseph A. Czagas , George Bajor , Leonel Enriquez , Chris A. McCarty
发明人： Joseph A. Czagas , George Bajor , Leonel Enriquez , Chris A. McCarty
IPC分类号： H01L2976
CPC分类号： H01L28/20 , H01L27/016 , H01L27/0802 , Y10S257/904
摘要： A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.
摘要翻译：通过在覆盖衬底中的集成电路的第一电介质层上直接蚀刻或剥离而形成的第一薄膜电阻器。第二薄膜电阻器由与第一电阻器不同的材料组成，通过在第一介电层上或在第一介电层上的第二介电层上直接蚀刻或剥离而形成。第一和第二薄膜电阻器与诸如其它电阻器或集成电路的另一电子器件互连。

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