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1. 发明申请

US20110170334A1 NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING 有权
标题翻译：非易失性存储器，存储器系统和驱动方法
公开(公告)号：US20110170334A1
公开(公告)日：2011-07-14
申请号：US13053471
申请日：2011-03-22
申请人： Joon-Min PARK , Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO , Hui-Kwon SEO
发明人： Joon-Min PARK , Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO , Hui-Kwon SEO
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元外部提供的升压电压。

2. 发明申请

US20090161419A1 NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING 失效
标题翻译：非易失性存储器，存储器系统和驱动方法
公开(公告)号：US20090161419A1
公开(公告)日：2009-06-25
申请号：US12339204
申请日：2008-12-19
申请人： Joon-Min PARK , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
发明人： Joon-Min PARK , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元使用外部提供的升压电压。

3. 发明申请

US20080175036A1 RESISTANCE RANDOM ACCESS MEMORY HAVING COMMON SOURCE LINE 有权
标题翻译：具有普通源线的电阻随机存取存储器
公开(公告)号：US20080175036A1
公开(公告)日：2008-07-24
申请号：US11964142
申请日：2007-12-26
申请人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
发明人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
摘要翻译：具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个源线。存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。在存储单元写入操作中，将正电压施加到源极线。通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

4. 发明申请

US20110103134A1 RESISTANCE RANDOM ACCESS MEMORY HAVING COMMON SOURCE LINE 审中-公开
标题翻译：具有普通源线的电阻随机存取存储器
公开(公告)号：US20110103134A1
公开(公告)日：2011-05-05
申请号：US13004251
申请日：2011-01-11
申请人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
发明人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
IPC分类号： G11C11/40
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the level of the positive source voltage to a selected bit line via the first write path when writing data having the first state in the memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the memory cell.
摘要翻译：一种方法通过第一和第二写入路径将数据写入电阻随机存取存储器（RRAM）存储单元，并且包括：对所选择的源极线施加正的源极电压，将字线驱动电压施加到所选择的字线，并且当写入数据时，通过第一写入路径将正的源极电压的电平至少两倍的电压施加到所选择的位线在存储单元中具有第一状态，并且当在存储单元中写入具有第二状态的数据时，经由第二写入路径将接地电压施加到所选择的位线。

5. 发明申请

US20080273365A1 NONVOLATILE MEMORY DEVICE HAVING TWIN MEMORY CELLS 有权
标题翻译：具有两个存储单元的非易失存储器件
公开(公告)号：US20080273365A1
公开(公告)日：2008-11-06
申请号：US12107985
申请日：2008-04-23
申请人： Sang-Beom KANG , Woo-Yeong CHO , Hyung-Rok OH , Joon-Min PARK
发明人： Sang-Beom KANG , Woo-Yeong CHO , Hyung-Rok OH , Joon-Min PARK
IPC分类号： G11C5/02
CPC分类号： G11C13/003 , G11C11/14 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile memory device includes multiple first bit lines extending in a first direction, multiple word lines formed on the first bit lines and extending in a second direction different from the first direction, and multiple second bit lines, formed on the word lines and extending in the first direction. The nonvoliative memory device also includes multiple twin memory cells, each of which includes a first memory cell coupled between a first bit line and a word line and a second memory cell coupled between the word line and a second bit line. The first and second memory cells store different data.
摘要翻译：非易失性存储器件包括沿第一方向延伸的多个第一位线，形成在第一位线上并在与第一方向不同的第二方向上延伸的多个字线以及形成在字线上并在字线上延伸的多个第二位线第一个方向。非易失性存储器件还包括多个双存储器单元，每个存储单元包括耦合在第一位线和字线之间的第一存储器单元和耦合在字线和第二位线之间的第二存储单元。第一和第二存储单元存储不同的数据。

6. 发明申请

US20080175031A1 MEMORY CELL OF A RESISTIVE SEMICONDUCTOR MEMORY DEVICE, A RESISTIVE SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STACK STRUCTURE, AND RELATED METHODS 有权
标题翻译：电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法
公开(公告)号：US20080175031A1
公开(公告)日：2008-07-24
申请号：US12015624
申请日：2008-01-17
申请人： Joon-Min PARK , Sang-Beom KANG , Hyung-Rok OH , Woo-Yeong CHO
发明人： Joon-Min PARK , Sang-Beom KANG , Hyung-Rok OH , Woo-Yeong CHO
IPC分类号： G11C5/02 , G11C11/21
CPC分类号： G11C5/02 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C2213/71 , G11C2213/72
摘要： A memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods are provided. The memory cell of a resistive semiconductor memory device includes a twin cell, wherein the twin cell stores data values representing one bit of data. The twin cell includes a main unit cell connected to a main bit line and a word line, and a sub unit cell connected to a sub bit line and the word line. Also, the main unit cell includes a first variable resistor and a first diode, and the sub unit cell includes a second variable resistor and a second diode.
摘要翻译：提供了电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法。电阻半导体存储器件的存储单元包括双胞胎，其中双胞胎存储表示一位数据的数据值。双胞胎单元包括连接到主位线和字线的主单元，以及连接到子位线和字线的子单元。此外，主单元包括第一可变电阻器和第一二极管，并且子单元电池包括第二可变电阻器和第二二极管。

7. 发明申请

US20080068903A1 PRAM PERFORMING PROGRAM LOOP OPERATION AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译： PRAM执行程序循环操作及其编程方法
公开(公告)号：US20080068903A1
公开(公告)日：2008-03-20
申请号：US11853955
申请日：2007-09-12
申请人： Joon-Min PARK , Du-Eung KIM
发明人： Joon-Min PARK , Du-Eung KIM
IPC分类号： G11C7/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0069 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2213/79
摘要： A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data programmed in the memory cell array and performing a program verify operation on the data, and a program loop control unit storing program verification result for the test cell at each program loop during test operation and generating the program pulse according to the program verification result to control the start of the program loop during normal operation.
摘要翻译：公开了PRAM和编程方法。 PRAM包括存储单元阵列，其包括测试单元，施加编程脉冲并向存储单元阵列提供编程电流的写入驱动器，读取在存储单元阵列中编程的数据并执行程序验证操作的读出放大和验证电路以及程序循环控制单元，其在测试操作期间在每个程序循环处存储测试单元的程序验证结果，并根据程序验证结果产生编程脉冲，以控制正常操作期间程序循环的开始。

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