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1. 发明申请

US20110170334A1 NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING 有权
标题翻译：非易失性存储器，存储器系统和驱动方法
公开(公告)号：US20110170334A1
公开(公告)日：2011-07-14
申请号：US13053471
申请日：2011-03-22
申请人： Joon-Min PARK , Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO , Hui-Kwon SEO
发明人： Joon-Min PARK , Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO , Hui-Kwon SEO
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元外部提供的升压电压。

2. 发明申请

US20080068903A1 PRAM PERFORMING PROGRAM LOOP OPERATION AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译： PRAM执行程序循环操作及其编程方法
公开(公告)号：US20080068903A1
公开(公告)日：2008-03-20
申请号：US11853955
申请日：2007-09-12
申请人： Joon-Min PARK , Du-Eung KIM
发明人： Joon-Min PARK , Du-Eung KIM
IPC分类号： G11C7/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0069 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2213/79
摘要： A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data programmed in the memory cell array and performing a program verify operation on the data, and a program loop control unit storing program verification result for the test cell at each program loop during test operation and generating the program pulse according to the program verification result to control the start of the program loop during normal operation.
摘要翻译：公开了PRAM和编程方法。 PRAM包括存储单元阵列，其包括测试单元，施加编程脉冲并向存储单元阵列提供编程电流的写入驱动器，读取在存储单元阵列中编程的数据并执行程序验证操作的读出放大和验证电路以及程序循环控制单元，其在测试操作期间在每个程序循环处存储测试单元的程序验证结果，并根据程序验证结果产生编程脉冲，以控制正常操作期间程序循环的开始。

3. 发明申请

US20110026306A1 RESISTANCE VARIABLE MEMORY DEVICE REDUCING WORD LINE VOLTAGE 有权
标题翻译：电阻可变存储器件减少字线电压
公开(公告)号：US20110026306A1
公开(公告)日：2011-02-03
申请号：US12903279
申请日：2010-10-13
申请人： Byung-Gil Choi , Du-Eung KIM
发明人： Byung-Gil Choi , Du-Eung KIM
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.
摘要翻译：电阻可变存储器件包括存储单元阵列，读出放大器电路和列选择电路。存储单元阵列包括多个块单元和多个字线驱动器，其中每个块单元连接在相邻字线驱动器之间并且包括多个存储块。读出放大器电路包括多个读出放大器单元，其中每个读出放大器单元向对应的块单元提供读取电流并且包括多个读出放大器。列选择电路连接在存储单元阵列和读出放大器电路之间，并响应于列选择信号选择多个存储块中的至少一个，以将读出的电流从读出放大器电路施加到所选存储块。

4. 发明申请

US20090027956A1 RESISTANCE VARIABLE MEMORY DEVICE REDUCING WORD LINE VOLTAGE 有权
标题翻译：电阻可变存储器件减少字线电压
公开(公告)号：US20090027956A1
公开(公告)日：2009-01-29
申请号：US12245929
申请日：2008-10-06
申请人： Byung-Gil CHOI , Du-Eung KIM
发明人： Byung-Gil CHOI , Du-Eung KIM
IPC分类号： G11C11/00 , G11C8/08
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.
摘要翻译：电阻可变存储器件包括存储单元阵列，读出放大器电路和列选择电路。存储单元阵列包括多个块单元和多个字线驱动器，其中每个块单元连接在相邻字线驱动器之间并且包括多个存储块。读出放大器电路包括多个读出放大器单元，其中每个读出放大器单元向对应的块单元提供读取电流并且包括多个读出放大器。列选择电路连接在存储单元阵列和读出放大器电路之间，并响应于列选择信号选择多个存储块中的至少一个，以将读出的电流从读出放大器电路施加到所选存储块。

5. 发明申请

US20090046500A1 APPARATUS AND METHOD OF NONVOLATILE MEMORY DEVICE HAVING THREE-LEVEL NONVOLATILE MEMORY CELLS 有权
标题翻译：具有三级非易失性记忆细胞的非易失性记忆装置的装置和方法
公开(公告)号：US20090046500A1
公开(公告)日：2009-02-19
申请号：US12187550
申请日：2008-08-07
申请人： Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO
发明人： Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/0092 , G11C2211/5622 , G11C2211/5641 , G11C2213/72 , G11C2213/79
摘要： An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.
摘要翻译：使用具有三电平非易失性存储单元的非易失性存储器件的装置和操作方法在非易失性存储单元中存储多于一位的数据。此外，可以通过写入验证操作来选择性地写入数据，从而提高写入操作的可靠性。操作方法包括提供具有第一至第三非易失性存储单元的存储单元阵列，其中每个存储单元能够分别在第一数据与第一至第三电阻电平对应的第三数据之间存储一个存储单元。每个阻力水平彼此不同。在写入操作的第一间隔期间，分别将第一和第三数据写入第一和第三非易失性存储器单元。在写入操作的第二间隔期间，将第二数据写入第二非易失性存储单元。

6. 发明申请

US20090237986A1 NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20090237986A1
公开(公告)日：2009-09-24
申请号：US12406441
申请日：2009-03-18
申请人： Byung-Gil Choi , Du-Eung KIM
发明人： Byung-Gil Choi , Du-Eung KIM
IPC分类号： G11C11/00 , G11C8/08 , G11C8/00
CPC分类号： G11C8/08 , G11C8/14 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2029/1202
摘要： A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件，其具有减小的布局尺寸和改进的性能。所述非易失性存储器件包括：主字线; 多个子字线，其中每个子字线连接到多个非易失性存储器单元; 以及区域字线驱动器，其控制所述多个子字线的电压电平，其中所述部分字线驱动器包括连接到所述多个子字线中的每一个的多个下拉元件，以及公共节点和选择元件其连接到公共节点和主字线。

7. 发明申请

US20090003049A1 PHASE CHANGE MEMORY DEVICE AND PROGRAM METHOD THEREOF 有权
标题翻译：相变存储器件及其程序方法
公开(公告)号：US20090003049A1
公开(公告)日：2009-01-01
申请号：US12168742
申请日：2008-07-07
申请人： Kwang-Jin LEE , Du-Eung KIM , Sang-Beom KANG , Woo-Yeong CHO
发明人： Kwang-Jin LEE , Du-Eung KIM , Sang-Beom KANG , Woo-Yeong CHO
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.
摘要翻译：相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路编程间隔。泵电路响应于外部控制信号在编程间隔之前被激活。

8. 发明申请

US20080291715A1 NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS 审中-公开
标题翻译：使用可变电阻材料的非易失性存储器件
公开(公告)号：US20080291715A1
公开(公告)日：2008-11-27
申请号：US12116295
申请日：2008-05-07
申请人： Mu-Hui PARK , Kwang-Jin LEE , Du-Eung KIM , Hye-Jin KIM , Woo-Yeong CHO
发明人： Mu-Hui PARK , Kwang-Jin LEE , Du-Eung KIM , Hye-Jin KIM , Woo-Yeong CHO
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0038 , G11C7/04 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C29/02 , G11C29/026 , G11C29/028
摘要： A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.
摘要翻译：非易失性存储器件包括非易失性存储单元，读取电路和控制偏置产生电路。非易失性存储单元具有根据存储的数据而改变的电阻水平。读取电路通过接收控制偏置来读取非易失性存储单元的电阻电平，并且基于控制偏压向非易失性存储单元提供读取偏置。控制偏置产生电路接收输入偏置，基于输入偏置产生控制偏压，并将控制偏压提供给读取电路。对输入偏置的控制偏置的斜率小于1。

9. 发明申请

US20100085799A1 METHOD OF DRIVING MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE AND MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE 有权
标题翻译：驱动多级可变电阻记忆装置和多级可变电阻记忆装置的方法
公开(公告)号：US20100085799A1
公开(公告)日：2010-04-08
申请号：US12632018
申请日：2009-12-07
申请人： Woo-Yeong CHO , Ki-Sung KIM , Du-Eung KIM , Kwang-Jin LEE , Jun-Soo BAE
发明人： Woo-Yeong CHO , Ki-Sung KIM , Du-Eung KIM , Kwang-Jin LEE , Jun-Soo BAE
IPC分类号： G11C11/00 , G11C7/02 , G11C7/00
CPC分类号： G11C11/5678 , G11C7/04 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2211/5634
摘要： Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.
摘要翻译：公开了一种驱动多电平可变电阻存储器件的方法。驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定的电阻窗，预期电阻窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少的量的写入电流，以便改变可变电阻存储单元的电阻。

10. 发明申请

US20090291522A1 LAYOUT STRUCTURE IN SEMICONDUCTOR MEMORY DEVICE COMPRISING GLOBAL WORD LINES, LOCAL WORD LINES, GLOBAL BIT LINES AND LOCAL BIT LINES 有权
标题翻译：包含全球字线，本地字线，全球位线和本地位线的半导体存储器件中的布局结构
公开(公告)号：US20090291522A1
公开(公告)日：2009-11-26
申请号：US12509617
申请日：2009-07-27
申请人： Hyung-Rok OH , Sang-Beom KANG , Du-Eung KIM
发明人： Hyung-Rok OH , Sang-Beom KANG , Du-Eung KIM
IPC分类号： H01L21/06 , G11C5/02
CPC分类号： G11C7/18 , G11C5/063 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
摘要翻译：提供了具有层次结构的半导体存储器件中的线路布局结构和方法。在具有全局字线和本地字线以及全局位线和局部位线的半导体存储器件中，并且单独地布置全局全局字线，局部字线，全局位线和局部位在至少三层中的导电层上线; 全局字线，本地字线，全局位线和局部位线中的至少两个在一个导电层上一并设置。构成半导体存储器件的信号线以分层结构设置，从而可以获得有利地具有高集成度，高速度和高性能的半导体存储器件。

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