专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08964488B2 Non-volatile memory device using variable resistance element with an improved write performance 有权
标题翻译：使用可变电阻元件的非易失性存储器件具有改进的写入性能
公开(公告)号：US08964488B2
公开(公告)日：2015-02-24
申请号：US13470617
申请日：2012-05-14
申请人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
发明人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
IPC分类号： G11C5/14 , G11C7/10 , G11C11/22 , G11C13/00 , G11C8/10
CPC分类号： G11C5/14 , G11C7/1078 , G11C7/1096 , G11C8/10 , G11C11/22 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/72
摘要： A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件。非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，被配置为产生第一电压的第一电压发生器，被配置为接收具有高于第一电压的电平的外部电压的电压焊盘写入驱动器，被配置为被提供有所述外部电压并被配置为向从所述存储单元阵列中选择的所述多个非易失性存储器单元写入数据; 感测放大器，被配置为被提供有外部电压并且被配置为从从存储单元阵列中选择的多个非易失性存储器单元读取数据;行解码器和列解码器，被配置为选择多个非易失性存储器包括在存储单元阵列中的单元，行解码器被提供有第一电压，并且列解码器被提供有外部电压。

2. 发明申请

US20130039124A1 PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND RELATED METHODS OF OPERATION 有权
标题翻译：相变随机访问存储器件及相关操作方法
公开(公告)号：US20130039124A1
公开(公告)日：2013-02-14
申请号：US13655666
申请日：2012-10-19
申请人： Hye-jin KIM , Kwang-jin LEE , Du-eung KIM
发明人： Hye-jin KIM , Kwang-jin LEE , Du-eung KIM
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092
摘要： A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.
摘要翻译：操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

3. 发明授权

US08254159B2 Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation 有权
标题翻译：对执行读写操作的非易失性半导体存储器件的位线进行放电的方法
公开(公告)号：US08254159B2
公开(公告)日：2012-08-28
申请号：US12662512
申请日：2010-04-21
申请人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
发明人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/72 , G11C2213/79
摘要： In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. The method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.
摘要翻译：在执行读写操作的非易失性半导体存储器件的放电位线的方法中。该方法包括在第一周期内基于写入命令将全局写入位线放电到接地电压。该方法还包括在第二周期期间将全局写入位线的放电电压保持在接地电压中。

4. 发明授权

US08194442B2 Apparatus and systems using phase change memories 有权
标题翻译：使用相变存储器的装置和系统
公开(公告)号：US08194442B2
公开(公告)日：2012-06-05
申请号：US13091238
申请日：2011-04-21
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要翻译：提供了使用相变存储器件的装置和系统。相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多个复位线中相应的一个。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

5. 发明授权

US08116117B2 Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device 有权
标题翻译：驱动多级可变电阻式存储器件和多级可变电阻式存储器件的方法
公开(公告)号：US08116117B2
公开(公告)日：2012-02-14
申请号：US12632018
申请日：2009-12-07
申请人： Woo-Yeong Cho , Ki-Sung Kim , Du-Eung Kim , Kwang-Jin Lee , Jun-Soo Bae
发明人： Woo-Yeong Cho , Ki-Sung Kim , Du-Eung Kim , Kwang-Jin Lee , Jun-Soo Bae
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C7/04 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2211/5634
摘要： Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.
摘要翻译：公开了一种驱动多电平可变电阻存储器件的方法。一种驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定电阻窗，预期电阻窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少量的写入电流，以便改变可变电阻存储单元的电阻。

6. 发明授权

US08102704B2 Method of preventing coupling noises for a non-volatile semiconductor memory device 有权
标题翻译：防止非易失性半导体存储器件耦合噪声的方法
公开(公告)号：US08102704B2
公开(公告)日：2012-01-24
申请号：US12662247
申请日：2010-04-07
申请人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
发明人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
IPC分类号： G11C16/32
CPC分类号： G11C7/04 , G11C7/18 , G11C7/22 , G11C16/32 , G11C2207/002
摘要： Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.
摘要翻译：公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。基于检查结果修改写操作信号。

7. 发明授权

US08098518B2 Nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08098518B2
公开(公告)日：2012-01-17
申请号：US12476875
申请日：2009-06-02
申请人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
发明人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.
摘要翻译：非易失性存储器件可以包括具有排列成行和列阵列的多个非易失性存储单元的存储单元阵列。多个位线中的每一个可以耦合到阵列的各个列中的非易失性存储器单元，并且多个列选择开关中的每一个可以耦合到相应的一个位线。列解码器可以耦合到多个列选择开关，并且列解码器可以被配置为使用具有施加到列选择中的第一个的第一信号电平的第一列选择信号来选择位线中的第一位开关。列解码器还可以被配置为使用具有第二信号电平的第二列选择信号来选择位线中的第二位，其中第二信号电平施加到第二信号电平不同于第一信号电平的列选择开关中的第二信号电平。

8. 发明申请

US20110110172A1 Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 有权
公开(公告)号：US20110110172A1
公开(公告)日：2011-05-12
申请号：US12929349
申请日：2011-01-18
申请人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
发明人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C13/0064 , G11C7/1078 , G11C7/1096 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C15/00 , G11C2013/0078 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
摘要： At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

9. 发明授权

US07936619B2 Nonvolatile memory, memory system, and method of driving 失效
标题翻译：非易失性存储器，存储器系统和驾驶方法
公开(公告)号：US07936619B2
公开(公告)日：2011-05-03
申请号：US12339204
申请日：2008-12-19
申请人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
发明人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元使用外部提供的升压电压。

10. 发明授权

US07920432B2 Semiconductor device having resistance based memory array, method of reading, and systems associated therewith 有权
公开(公告)号：US07920432B2
公开(公告)日：2011-04-05
申请号：US12292897
申请日：2008-11-28
申请人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
发明人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
IPC分类号： G11C7/00
CPC分类号： G11C13/0061 , G11C7/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/004
摘要： One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式