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1. 发明授权

US06487125B2 Integrated circuit having an EEPROM and flash EPROM 有权
公开(公告)号：US06487125B2
公开(公告)日：2002-11-26
申请号：US10099291
申请日：2002-03-12
申请人： Eungjoon Park , Ali Pourkeramati
发明人： Eungjoon Park , Ali Pourkeramati
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , G11C16/0408
摘要： In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.

2. 发明授权

US06667906B2 Integrated circuit having an EEPROM and flash EPROM using a memory cell with source-side programming 有权
公开(公告)号：US06667906B2
公开(公告)日：2003-12-23
申请号：US10100508
申请日：2002-03-14
申请人： Eungjoon Park , Ali Pourkeramati
发明人： Eungjoon Park , Ali Pourkeramati
IPC分类号： G11C1134
CPC分类号： G11C16/0416
摘要： In accordance with one embodiment of the present invention, a non-volatile integrated circuit memory includes a flash EPROM array having a first plurality of memory cells, and an EEPROM array having a second plurality of memory cells arranged along rows and columns. Each of the first and second plurality of memory cells has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a floating gate and a select gate. The EEPROM array further includes a plurality of data lines each being coupled to the drain regions of a plurality of cells along at least a portion of a column of cells, and a plurality of source lines each being coupled to the source regions of a plurality of cells along at least a portion of a row of cells.

3. 发明授权

US07781890B2 Structure and method for parallel testing of dies on a semiconductor wafer 有权
标题翻译：用于半导体晶片上的管芯并联测试的结构和方法
公开(公告)号：US07781890B2
公开(公告)日：2010-08-24
申请号：US11614241
申请日：2006-12-21
申请人： Ali Pourkeramati , Eungjoon Park
发明人： Ali Pourkeramati , Eungjoon Park
IPC分类号： H01L23/48
CPC分类号： G01R31/2884 , H01L22/32 , H01L2224/05554
摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.
摘要翻译：根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘以及用于接收测试控制信号的第三接触焊盘。第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

4. 发明授权

US06288938B1 Flash memory architecture and method of operation 有权
标题翻译：闪存架构和操作方法
公开(公告)号：US06288938B1
公开(公告)日：2001-09-11
申请号：US09433245
申请日：1999-11-03
申请人： Eungjoon Park , Ali Pourkeramati
发明人： Eungjoon Park , Ali Pourkeramati
IPC分类号： G11C1400
CPC分类号： G11C16/0416 , H01L29/7886
摘要： A flash memory device and its method of operation provide for selective, e.g., bit-by-bit, erase operation resulting in much narrower distribution for erase threshold voltage VTE. Latches that couple to the array are set or reset depending on cell content during erase verify. The output of the latches are then applied to selected cells to perform erase. The flash architecture allows for bit-by-bit erase verify operation resulting in a tighter VTE distribution and elimination of the need for preprogramming. In a preferred embodiment, the flash cell is programmed by CHE tunneling and erased by FN tunneling both occurring on the same side (e.g., drain side) of the cell transistor.
摘要翻译：闪速存储器件及其操作方法提供了选择性的，例如逐位的擦除操作，导致擦除阈值电压VTE的分布更窄。耦合到阵列的锁存器根据擦除验证期间的单元格内容设置或复位。然后将锁存器的输出应用于选定的单元进行擦除。闪存架构允许逐位擦除验证操作，导致更紧密的VTE分发和消除对预编程的需要。在优选实施例中，闪存单元通过CHE隧道编程，并通过发生在单元晶体管的同一侧（例如，漏极侧）上的FN隧道擦除。

5. 发明授权

US07173444B2 Structure and method for parallel testing of dies on a semiconductor wafer 失效
标题翻译：用于半导体晶片上的管芯并联测试的结构和方法
公开(公告)号：US07173444B2
公开(公告)日：2007-02-06
申请号：US10340558
申请日：2003-01-09
申请人： Ali Pourkeramati , Eungjoon Park
发明人： Ali Pourkeramati , Eungjoon Park
IPC分类号： G01R31/02 , G01R31/06
CPC分类号： G01R31/2884 , H01L22/32 , H01L2224/05554
摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.
摘要翻译：根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘和用于接收测试控制信号的第三接触焊盘。第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

6. 发明授权

US07449350B2 Structure and method for parallel testing of dies on a semiconductor wafer 有权
标题翻译：用于半导体晶片上的管芯并联测试的结构和方法
公开(公告)号：US07449350B2
公开(公告)日：2008-11-11
申请号：US11614252
申请日：2006-12-21
申请人： Ali Pourkeramati , Eungjoon Park
发明人： Ali Pourkeramati , Eungjoon Park
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/32 , H01L2224/05554
摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.
摘要翻译：根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘和用于接收测试控制信号的第三接触焊盘。第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

7. 发明申请

US20070102701A1 Structure and Method for Parallel Testing of Dies on a Semiconductor Wafer 有权
标题翻译：半导体晶片上芯片并联测试的结构和方法
公开(公告)号：US20070102701A1
公开(公告)日：2007-05-10
申请号：US11614241
申请日：2006-12-21
申请人： Ali Pourkeramati , Eungjoon Park
发明人： Ali Pourkeramati , Eungjoon Park
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , H01L22/32 , H01L2224/05554
摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.
摘要翻译：根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘以及用于接收测试控制信号的第三接触焊盘。第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

8. 发明申请

US20070099312A1 STRUCTURE AND METHOD FOR PARALLEL TESTING OF DIES ON A SEMICONDUCTOR WAFER 有权
标题翻译：在半导体晶片上并行测试晶体的结构和方法
公开(公告)号：US20070099312A1
公开(公告)日：2007-05-03
申请号：US11614252
申请日：2006-12-21
申请人： Ali Pourkeramati , Eungjoon Park
发明人： Ali Pourkeramati , Eungjoon Park
IPC分类号： H01L21/00
CPC分类号： G01R31/2884 , H01L22/32 , H01L2224/05554
摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.
摘要翻译：根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘和用于接收测试控制信号的第三接触焊盘。第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

9. 发明授权

US06501684B1 Integrated circuit having an EEPROM and flash EPROM 有权
公开(公告)号：US06501684B1
公开(公告)日：2002-12-31
申请号：US09668431
申请日：2000-09-22
申请人： Eungjoon Park , Ali Pourkeramati
发明人： Eungjoon Park , Ali Pourkeramati
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , G11C16/0408
摘要： In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.

10. 发明授权

US08638633B2 Apparatus and method for external charge pump on flash memory module 有权
标题翻译：闪存模块外部电荷泵的装置和方法
公开(公告)号：US08638633B2
公开(公告)日：2014-01-28
申请号：US13098389
申请日：2011-04-29
申请人： Allan Parker , Ali Pourkeramati , Arthur Benjamin Oliver
发明人： Allan Parker , Ali Pourkeramati , Arthur Benjamin Oliver
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C16/06
摘要： A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages.
摘要翻译：提供存储器模块。存储器模块包括管芯封装和在管芯封装外部的电荷泵。每个管芯封装包括闪存器件，并且每个闪存器件包括耦合到位线的位线和存储器单元。电荷泵提供电荷泵电压，其被选择性地提供给每个管芯封装中的每个闪存器件中的位线。

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