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1. 发明授权

US06660645B1 Process for etching an organic dielectric using a silyated photoresist mask 有权
标题翻译：使用硅化光致抗蚀剂掩模蚀刻有机电介质的方法
公开(公告)号：US06660645B1
公开(公告)日：2003-12-09
申请号：US10051725
申请日：2002-01-17
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H07L21302
CPC分类号： H01L21/31144
摘要： A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.
摘要翻译：用于形成半导体器件的工艺可以包括在衬底上形成有机电介质层，在有机介电层上形成保护层，在保护层上形成光致抗蚀剂掩模，并使光刻胶掩模进行硅化。使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻保护层，然后使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻有机介电层。金属可以沉积在蚀刻在有机介电层中的空隙中以形成布线，接触或通孔。

2. 发明授权

US06689541B1 Process for forming a photoresist mask 有权
标题翻译：光刻胶掩模形成工艺
公开(公告)号：US06689541B1
公开(公告)日：2004-02-10
申请号：US09884182
申请日：2001-06-19
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： G03C500
CPC分类号： G03F7/38 , G03F7/265 , G03F7/40
摘要： In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.
摘要翻译：在形成光致抗蚀剂掩模的工艺中，将光致抗蚀剂层施加到基底上。在光致抗蚀剂层中形成硅化层。硅酸盐化区域的特征对应于要形成的光致抗蚀剂掩模的特征。然后蚀刻光致抗蚀剂层以在硅化区域下方形成光致抗蚀剂基底。蚀刻光致抗蚀剂基底以从其侧面去除材料，使得它比斯里芬特区域变窄。然后除去硅酸盐化区域，在基材上留下光刻胶掩模。

3. 发明授权

US06563221B1 Connection structures for integrated circuits and processes for their formation 失效
标题翻译：集成电路的连接结构及其形成过程
公开(公告)号：US06563221B1
公开(公告)日：2003-05-13
申请号：US10081982
申请日：2002-02-21
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L2348
CPC分类号： H01L21/76885 , H01L21/76831 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.
摘要翻译：在用于在集成电路中形成连接结构的方法中，第一导电材料沉积在衬底上并被图案化以形成与衬底的导电元件电接触的导电柱。电介质形成在衬底和导电柱上。在电介质中形成沟槽以暴露导电柱的顶部，并且第二导电材料镶嵌在沟槽中以形成与导电柱电接触的布线。衬底的导电元件可以是半导体器件或布线，接触或通孔的元件。第一导电材料可以是铝，第二导电材料可以是铜。电介质可以形成为单层，并且可以是有机低k电介质。还公开了相关的连接结构。

4. 发明授权

US06753266B1 Method of enhancing gate patterning properties with reflective hard mask 有权
标题翻译：用反射硬掩模增强栅极图案化性能的方法
公开(公告)号：US06753266B1
公开(公告)日：2004-06-22
申请号：US09845654
申请日：2001-04-30
申请人： Todd P. Lukanc , Scott A. Bell , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Todd P. Lukanc , Scott A. Bell , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21309
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/823828
摘要： An exemplary method of fabricating an integrated circuit can include depositing a reflective metal material layer over a layer of polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etching the reflective metal material layer according to the pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating.
摘要翻译：制造集成电路的示例性方法可以包括在多晶硅层上沉积反射金属材料层，在反射金属材料层上沉积抗反射涂层，修整蚀刻抗反射涂层以形成图案，蚀刻反射金属材料层，并且使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。

5. 发明授权

US06566214B1 Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer 失效
标题翻译：通过退火金属层以形成金属硅化物并且使用金属硅化物作为硬掩模来制造半导体器件以图案化多晶硅层的方法
公开(公告)号：US06566214B1
公开(公告)日：2003-05-20
申请号：US10047036
申请日：2002-01-17
申请人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
IPC分类号： H01L213213
CPC分类号： H01L21/28123
摘要： A method of making a semiconductor device is provided. A polysilicon layer is formed over a substrate and a metal layer is formed on the polysilicon layer. The metal layer and the polysilicon layer are annealed to form a metal silicide layer on the polysilicon layer. The metal silicide layer is patterned and the polysilicon layer is then patterned using the patterned metal silicide layer as a mask. The patterned metal silicide and polysilicon layers may be used as a gate electrode of a MOSFET.
摘要翻译：提供制造半导体器件的方法。在衬底上形成多晶硅层，并且在多晶硅层上形成金属层。退火金属层和多晶硅层，以在多晶硅层上形成金属硅化物层。图案化金属硅化物层，然后使用图案化的金属硅化物层作为掩模来对多晶硅层进行构图。图案化的金属硅化物和多晶硅层可以用作MOSFET的栅电极。

6. 发明授权

US06358856B1 Bright field image reversal for contact hole patterning 有权
标题翻译：接触孔图案的亮场图像反转
公开(公告)号：US06358856B1
公开(公告)日：2002-03-19
申请号：US09716215
申请日：2000-11-21
申请人： Christopher F. Lyons , Ramkumar Subramanian , Marina V. Plat , Todd P. Lukanc
发明人： Christopher F. Lyons , Ramkumar Subramanian , Marina V. Plat , Todd P. Lukanc
IPC分类号： H01L21311
CPC分类号： H01L21/31144
摘要： A method of forming a small contact hole uses a bright field mask to form a small cylinder in a positive resist layer. A negative resist layer is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole located where the small cylinder was previously located.
摘要翻译：形成小接触孔的方法使用亮场掩模在正抗蚀剂层中形成小圆筒。在小圆筒周围形成负的抗蚀剂层，然后被蚀刻或抛光回去，使得暴露在负性抗蚀剂层上方的小圆筒的顶部部分留下。负抗蚀剂层和小圆筒（正性抗蚀剂）暴露于光下，然后经受显影剂。剩下的是一个位于小圆柱之前所在的小接触孔。

7. 发明授权

US06448164B1 Dark field image reversal for gate or line patterning 失效
标题翻译：用于门或线图案的暗场图像反转
公开(公告)号：US06448164B1
公开(公告)日：2002-09-10
申请号：US09716216
申请日：2000-11-21
申请人： Christopher F. Lyons , Ramkumar Subramanian , Marina V. Plat , Todd P. Lukanc
发明人： Christopher F. Lyons , Ramkumar Subramanian , Marina V. Plat , Todd P. Lukanc
IPC分类号： H01L213205
CPC分类号： H01L21/0274 , H01L21/28123
摘要： A method of forming either a gate pattern or a line pattern in a resist by using a dark field mask and a combination of a negative photoresist and a positive photoresist. The dark field mask is used to create a hole within the positive photoresist, by exposing only a portion of the positive photoresist to light, and then by subjecting the positive photoresist to a developer. The negative photoresist is formed within the hole of the positive photoresist, and etched or polished so that it is only disposed within the hole. The negative photoresist and the positive photoresist are subjected to a flood light exposure, and then to a developer. This causes the positive photoresist to dissolve, leaving the negative photoresist, thereby providing a very-small-dimension resist pattern that can be used to form either a gate or a line for a semiconductor device.
摘要翻译：通过使用暗场掩模和负光致抗蚀剂和正性光致抗蚀剂的组合在抗蚀剂中形成栅极图案或线图案的方法。暗场掩模用于在正性光致抗蚀剂中产生孔，通过仅将一部分正性光致抗蚀剂暴露于光，然后通过使正性光致抗蚀剂经受显影剂。负光致抗蚀剂形成在正性光致抗蚀剂的孔内，并被蚀刻或抛光，使得其仅设置在孔内。对负性光致抗蚀剂和正性光致抗蚀剂进行泛光曝光，然后进行显影。这导致正性光致抗蚀剂溶解，留下负性光致抗蚀剂，从而提供可用于形成半导体器件的栅极或线的非常小的抗蚀剂图案。

8. 发明授权

US07368225B1 Two mask photoresist exposure pattern for dense and isolated regions 有权
标题翻译：两个掩模光刻胶曝光图案，用于密集和隔离的区域
公开(公告)号：US07368225B1
公开(公告)日：2008-05-06
申请号：US10925123
申请日：2004-08-24
申请人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
发明人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
IPC分类号： G03F7/00
CPC分类号： G03F1/00 , H01L21/76816
摘要： There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.
摘要翻译：提供了在第一层中制作多个特征的方法。在第一层上形成光致抗蚀剂层。光致抗蚀剂层中的密集区域在第一组照射条件下通过第一掩模曝光。在与第一组照明条件不同的第二组照明条件下，光致抗蚀剂层中的隔离区域通过不同于第一掩模的第二掩模曝光。曝光的光致抗蚀剂层被图案化，然后使用图案化的光致抗蚀剂层作为掩模来对第一层进行图案化。

9. 发明授权

US06803178B1 Two mask photoresist exposure pattern for dense and isolated regions 有权
标题翻译：两个掩模光刻胶曝光图案，用于密集和隔离的区域
公开(公告)号：US06803178B1
公开(公告)日：2004-10-12
申请号：US09887035
申请日：2001-06-25
申请人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eli Kim
发明人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eli Kim
IPC分类号： G03F700
CPC分类号： G03F1/00 , H01L21/76816
摘要： There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.
摘要翻译：提供了在第一层中制作多个特征的方法。在第一层上形成光致抗蚀剂层。光致抗蚀剂层中的密集区域在第一组照射条件下通过第一掩模曝光。在与第一组照明条件不同的第二组照明条件下，光致抗蚀剂层中的隔离区域通过不同于第一掩模的第二掩模曝光。曝光的光致抗蚀剂层被图案化，然后使用图案化的光致抗蚀剂层作为掩模来对第一层进行图案化。

10. 发明授权

US06548423B1 Multilayer anti-reflective coating process for integrated circuit fabrication 有权
标题翻译：用于集成电路制造的多层抗反射涂层工艺
公开(公告)号：US06548423B1
公开(公告)日：2003-04-15
申请号：US10047971
申请日：2002-01-16
申请人： Marina V. Plat , Christopher F. Lyons , Scott A. Bell , Todd P. Lukanc
发明人： Marina V. Plat , Christopher F. Lyons , Scott A. Bell , Todd P. Lukanc
IPC分类号： H01L2131
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/0332 , H01L21/28123 , H01L21/32139
摘要： A method utilizing a multilayer anti-reflective coating layer structure. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating.
摘要翻译：一种利用多层抗反射涂层结构的方法。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层上施加光致抗蚀剂。

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