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1. 发明授权

US07482962B2 Systems, methods, and apparatuses for digital wavelet generators for Multi-Resolution Spectrum Sensing of Cognitive Radio applications 失效
标题翻译：用于认知无线电应用的多分辨率频谱感测的数字小波发生器的系统，方法和装置
公开(公告)号：US07482962B2
公开(公告)日：2009-01-27
申请号：US11778565
申请日：2007-07-16
申请人： Taejoong Song , Jongmin Park , Youngsik Hur , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
发明人： Taejoong Song , Jongmin Park , Youngsik Hur , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
IPC分类号： H03M1/66
CPC分类号： H04L27/0004
摘要： Embodiments of the invention may provide for digital wavelet generators utilized in providing flexible spectrum-sensing resolutions for a Multi-Resolution Spectrum Sensing (MRSS) technique. Embodiments of the invention may provide for either multi-point or multi-rate digital wavelet generators. These digital wavelet generators may utilizing the same hardware resource optimally, and the various wavelet bases may be generated by changing the memory addressing schemes or clock speeds.
摘要翻译：本发明的实施例可以提供用于为多分辨率频谱感测（MRSS）技术提供灵活的频谱感测分辨率的数字小波发生器。本发明的实施例可以提供多点或多速率数字小波发生器。这些数字小波发生器可以最佳地利用相同的硬件资源，并且可以通过改变存储器寻址方案或时钟速度来生成各种小波基。

2. 发明申请

US20080024336A1 Systems, Methods, and Apparatuses for a Long Delay Generation Technique for Spectrum-Sensing of Cognitive Radios 失效
标题翻译：用于长时间生成技术的系统，方法和装置，用于认知无线电的频谱感知
公开(公告)号：US20080024336A1
公开(公告)日：2008-01-31
申请号：US11778557
申请日：2007-07-16
申请人： Jongmin Park , Taejoong Song , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
发明人： Jongmin Park , Taejoong Song , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
IPC分类号： H03M1/00
CPC分类号： H04B17/382
摘要： Embodiments of the present invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may comprise of an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.
摘要翻译：本发明的实施例可以提供用于认知无线电系统的频谱感测的长延迟发生器。长延迟发生器可以包括模数转换器（ADC），存储器元件和数模转换器（DAC）。存储器元件可以利用移位寄存器组或随机存取存储器（RAM）单元。长延迟发生器可以通过数字化接收的信号，延迟数字域中的接收信号，并将延迟的信号重建为模拟来提供可选择的延迟。然后可以使用模拟自相关技术将模拟延迟信号与原始输入信号进行比较或相关，以确定是否已识别或以其他方式检测到有意义的信号类型。

3. 发明授权

US07528751B2 Systems, methods, and apparatuses for a long delay generation technique for spectrum-sensing of cognitive radios 失效
标题翻译：用于认知无线电频谱感知的长延迟生成技术的系统，方法和装置
公开(公告)号：US07528751B2
公开(公告)日：2009-05-05
申请号：US11778557
申请日：2007-07-16
申请人： Jongmin Park , Taejoong Song , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
发明人： Jongmin Park , Taejoong Song , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
IPC分类号： H03M1/00
CPC分类号： H04B17/382
摘要： Embodiments of the invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may include an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.
摘要翻译：本发明的实施例可以提供用于认知无线电系统的频谱感测的长延迟发生器。长延迟发生器可以包括模数转换器（ADC），存储器元件和数模转换器（DAC）。存储器元件可以利用移位寄存器组或随机存取存储器（RAM）单元。长延迟发生器可以通过数字化接收的信号，延迟数字域中的接收信号，并将延迟的信号重建为模拟来提供可选择的延迟。然后可以使用模拟自相关技术将模拟延迟信号与原始输入信号进行比较或相关，以确定是否已识别或以其他方式检测到有意义的信号类型。

4. 发明申请

US20080034171A1 Systems, Methods, and Apparatuses for Digital Wavelet Generators for Multi-Resolution Spectrum Sensing of Cognitive Radio Applications 失效
标题翻译：用于数字小波发生器的系统，方法和装置，用于认知无线电应用的多分辨率频谱感测
公开(公告)号：US20080034171A1
公开(公告)日：2008-02-07
申请号：US11778565
申请日：2007-07-16
申请人： Taejoong Song , Jongmin Park , Youngsik Hur , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
发明人： Taejoong Song , Jongmin Park , Youngsik Hur , Kyutae Lim , Chang-Ho Lee , Jeongsuk Lee , Kihong Kim , Seongsoo Lee , Haksun Kim , Joy Laskar
IPC分类号： G06F12/00
CPC分类号： H04L27/0004
摘要： Embodiments of the invention may provide for digital wavelet generators utilized in providing flexible spectrum-sensing resolutions for a Multi-Resolution Spectrum Sensing (MRSS) technique. Embodiments of the invention may provide for either multi-point or multi-rate digital wavelet generators. These digital wavelet generators may utilizing the same hardware resource optimally, and the various wavelet bases may be generated by changing the memory addressing schemes or clock speeds.
摘要翻译：本发明的实施例可以提供用于为多分辨率频谱感测（MRSS）技术提供灵活的频谱感测分辨率的数字小波发生器。本发明的实施例可以提供多点或多速率数字小波发生器。这些数字小波发生器可以最佳地利用相同的硬件资源，并且可以通过改变存储器寻址方案或时钟速度来生成各种小波基。

5. 发明授权

US07768252B2 Systems and methods for determining sensing thresholds of a multi-resolution spectrum sensing (MRSS) technique for cognitive radio (CR) systems 有权
标题翻译：用于确定用于认知无线电（CR）系统的多分辨率频谱感测（MRSS）技术的感测阈值的系统和方法
公开(公告)号：US07768252B2
公开(公告)日：2010-08-03
申请号：US12034570
申请日：2008-02-20
申请人： Jongmin Park , Kyutae Lim , Chang-Ho Lee , Haksun Kim , Joy Laskar
发明人： Jongmin Park , Kyutae Lim , Chang-Ho Lee , Haksun Kim , Joy Laskar
IPC分类号： G01R23/00
CPC分类号： H04W8/005 , H04W16/14 , H04W16/22
摘要： Systems and methods may be provided for threshold determinations for spectrum sensing. The systems and methods may include receiving a false alarm rate, where the false alarm rate is associated with false occupancy identifications of a spectrum segment, determining a noise floor as a function of a noise figure and characteristics of a multi-resolution spectrum sensing (MRSS) window, and calculating a sensing threshold based at least in part upon the false alarm rate and the noise floor. The systems and methods may also include determining whether a portion of an RF spectrum is occupied based at least in part on the calculated sensing threshold.
摘要翻译：可以提供用于频谱感测的阈值确定的系统和方法。系统和方法可以包括接收误报率，其中误报率与频谱段的假占用标识相关联，确定作为噪声系数和多分辨率频谱感测特性（MRSS）的函数的本底噪声）窗口，并且至少部分地基于所述误报率和所述本底噪声来计算感测阈值。系统和方法还可以包括至少部分地基于所计算的感测阈值来确定RF频谱的一部分是否被占用。

6. 发明申请

US20100073052A1 FRACTIONAL RESOLUTION INTEGER-N FREQUENCY SYNTHESIZER 审中-公开
标题翻译：分数分解整数N频率合成器
公开(公告)号：US20100073052A1
公开(公告)日：2010-03-25
申请号：US12563790
申请日：2009-09-21
申请人： Jaehyouk Choi , Jongmin Park , Kyutae Lim , Chang-Ho Lee , Haksun Kim , Joy Laskar
发明人： Jaehyouk Choi , Jongmin Park , Kyutae Lim , Chang-Ho Lee , Haksun Kim , Joy Laskar
IPC分类号： H03L7/08
CPC分类号： H03L7/185 , H03L7/0891 , H03L2207/10
摘要： Embodiments of the invention may provide for a frequency synthesizer capable to generate an output signal in which the frequency is a fractional portion of the reference frequency without a fractional divider. Based on mathematical relationship (“relatively prime”) between the reference frequency and other injection frequencies mixed with the output signal of a voltage controlled oscillator, the synthesizer is able to generate signals evenly spaced in the frequency domain like Fractional-N PLLs. The synthesizer may include an Integer-N PLL, a SSB mixer, frequency dividers, and frequency multipliers. A Integer-N PLL may include a Phase and Frequency Detector, a Charge Pump, a Loop Filter and a Dual Modulus Divider. By not requiring a fractional divider, the frequency synthesizer is able to avoid adopting any compensation circuits such as Sigma-Delta modulator to suppress fractional spurs. Therefore, the chip area, power consumption and complexity will be reduced considerably.
摘要翻译：本发明的实施例可以提供能够产生输出信号的频率合成器，其中频率是参考频率的小数部分而没有分数分频器。基于与压控振荡器的输出信号混合的参考频率和其他注入频率之间的数学关系（“相对主要”），合成器能够在频域中产生均匀间隔的信号，如分数N PLL。合成器可以包括整数N PLL，SSB混频器，分频器和频率乘法器。整数N PLL可以包括相位和频率检测器，电荷泵，环路滤波器和双模数分频器。通过不需要分数分频器，频率合成器能够避免采用诸如Sigma-Delta调制器之类的任何补偿电路来抑制分数杂散。因此，芯片面积，功耗和复杂度将大大降低。

7. 发明申请

US20080214130A1 Systems and methods for determining Sensing Thresholds of a Multi-Resolution Spectrum Sensing (MRSS) technique for Cognitive Radio (CR) Systems 有权
标题翻译：用于确定用于认知无线电（CR）系统的多分辨率频谱感测（MRSS）技术的感测阈值的系统和方法
公开(公告)号：US20080214130A1
公开(公告)日：2008-09-04
申请号：US12034570
申请日：2008-02-20
申请人： Jongmin Park , Kyutae Lim , Chang-Ho Lee , Haksun Kim , Joy Laskar
发明人： Jongmin Park , Kyutae Lim , Chang-Ho Lee , Haksun Kim , Joy Laskar
IPC分类号： H04B1/18
CPC分类号： H04W8/005 , H04W16/14 , H04W16/22
摘要： Systems and methods may be provided for threshold determinations for spectrum sensing. The systems and methods may include receiving a false alarm rate, where the false alarm rate is associated with false occupancy identifications of a spectrum segment, determining a noise floor as a function of a noise figure and characteristics of a multi-resolution spectrum sensing (MRSS) window, and calculating a sensing threshold based at least in part upon the false alarm rate and the noise floor. The systems and methods may also include determining whether a portion of an RF spectrum is occupied based at least in part on the calculated sensing threshold.
摘要翻译：可以提供用于频谱感测的阈值确定的系统和方法。系统和方法可以包括接收误报率，其中误报率与频谱段的假占用标识相关联，确定作为噪声系数和多分辨率频谱感测特性（MRSS）的函数的本底噪声）窗口，并且至少部分地基于所述误报率和所述本底噪声来计算感测阈值。系统和方法还可以包括至少部分地基于所计算的感测阈值来确定RF频谱的一部分是否被占用。

8. 发明授权

US08760957B2 Non-volatile memory and method having a memory array with a high-speed, short bit-line portion 有权
标题翻译：具有具有高速，短位线部分的存储器阵列的非易失性存储器和方法
公开(公告)号：US08760957B2
公开(公告)日：2014-06-24
申请号：US13431670
申请日：2012-03-27
申请人： Seungpil Lee , Jongmin Park
发明人： Seungpil Lee , Jongmin Park
IPC分类号： G11C8/00 , G11C16/04 , G11C11/56
CPC分类号： G11C16/0483 , G11C7/18 , G11C11/5621 , G11C16/0425 , G11C16/0433 , G11C2211/5641
摘要： A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions.
摘要翻译：沿着列方向将非易失性存储器阵列分割成第一和第二部分。第一部分具有SLC存储单元，第二部分具有MLC存储单元。第一部分用作第二部分的快速缓存。通过耦合到与第一部分相邻的一组读/写电路，第一部分的读/写操作进一步增强，同时每个位线的列在第一和第二部分之间的连接处可切换地切断。以这种方式，截止位线的RC常数处于最小值，这通过读/写电路转换为更快的位线预充电。当第二部分工作时，其通过不切断第一和第二部分之间的连接处的每个位线来实现对该组读/写电路的访问。

9. 发明申请

US20130176777A1 Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Verify to Program Transition 有权
标题翻译： NAND闪存写操作期间均衡和调节源，阱和位线电平的充电循环：验证程序转换
公开(公告)号：US20130176777A1
公开(公告)日：2013-07-11
申请号：US13570779
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jongmin Park , Man Lung Mui
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jongmin Park , Man Lung Mui
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。考虑脉冲和验证阶段之间的间隔。对于脉冲之后的间隔，但是在建立验证条件之前，可以将源极，位线以及可能的阱电平相等化，然后在期望的DC电平进行调节。在验证阶段之后，但是在将存储器应用于下一个脉冲之前，源和位线电平可以均衡为直流电平。

10. 发明申请

US20130176776A1 Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Program to Verify Transition 有权
标题翻译：通过在NAND闪存的写入操作期间均衡和调节源，阱和位线电平进行充电循环：验证转换的程序
公开(公告)号：US20130176776A1
公开(公告)日：2013-07-11
申请号：US13570746
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。考虑脉冲和验证阶段之间的间隔。对于脉冲之后的间隔，但是在建立验证条件之前，可以将源极，位线以及可能的阱电平相等化，然后在期望的DC电平进行调节。在验证阶段之后，但是在将存储器应用于下一个脉冲之前，源和位线电平可以均衡为直流电平。

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