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    • 6. 发明申请
    • FRACTIONAL RESOLUTION INTEGER-N FREQUENCY SYNTHESIZER
    • 分数分解整数N频率合成器
    • US20100073052A1
    • 2010-03-25
    • US12563790
    • 2009-09-21
    • Jaehyouk ChoiJongmin ParkKyutae LimChang-Ho LeeHaksun KimJoy Laskar
    • Jaehyouk ChoiJongmin ParkKyutae LimChang-Ho LeeHaksun KimJoy Laskar
    • H03L7/08
    • H03L7/185H03L7/0891H03L2207/10
    • Embodiments of the invention may provide for a frequency synthesizer capable to generate an output signal in which the frequency is a fractional portion of the reference frequency without a fractional divider. Based on mathematical relationship (“relatively prime”) between the reference frequency and other injection frequencies mixed with the output signal of a voltage controlled oscillator, the synthesizer is able to generate signals evenly spaced in the frequency domain like Fractional-N PLLs. The synthesizer may include an Integer-N PLL, a SSB mixer, frequency dividers, and frequency multipliers. A Integer-N PLL may include a Phase and Frequency Detector, a Charge Pump, a Loop Filter and a Dual Modulus Divider. By not requiring a fractional divider, the frequency synthesizer is able to avoid adopting any compensation circuits such as Sigma-Delta modulator to suppress fractional spurs. Therefore, the chip area, power consumption and complexity will be reduced considerably.
    • 本发明的实施例可以提供能够产生输出信号的频率合成器,其中频率是参考频率的小数部分而没有分数分频器。 基于与压控振荡器的输出信号混合的参考频率和其他注入频率之间的数学关系(“相对主要”),合成器能够在频域中产生均匀间隔的信号,如分数N PLL。 合成器可以包括整数N PLL,SSB混频器,分频器和频率乘法器。 整数N PLL可以包括相位和频率检测器,电荷泵,环路滤波器和双模数分频器。 通过不需要分数分频器,频率合成器能够避免采用诸如Sigma-Delta调制器之类的任何补偿电路来抑制分数杂散。 因此,芯片面积,功耗和复杂度将大大降低。
    • 10. 发明申请
    • ADAPTIVE COMBINER ERROR CALIBRATION ALGORITHMS IN ALL-DIGITAL OUTPHASING TRANSMITTER
    • 全数字输出发生器中的自适应组合器错误校准算法
    • US20100074367A1
    • 2010-03-25
    • US12561890
    • 2009-09-17
    • Kwan-Woo KimKyutae LimChang-Ho LeeHaksun KimJoy Laskar
    • Kwan-Woo KimKyutae LimChang-Ho LeeHaksun KimJoy Laskar
    • H04L25/03H04L27/12
    • H04L27/361H03F1/0294H03F1/3247H03F3/24H03F2200/207H03F2200/336H03F2200/375H03F2201/3233
    • Systems and methods may include a signal component separator that receives a non-constant envelope input signal and at least one phase offset value, and generates first digital phase data and second digital phase data; at least one digital phase modulator that receives the first phase data and the second phase data and operates with a frequency synthesizer to generate a first component signal having a first constant envelope and a second component signal having a second constant envelope; at least one power amplifier that amplifies the first component signal and the second component signal; a non-isolated power combiner that combines the first amplified component signal and the second amplified component signal to generate an output signal having a non-constant envelope; and a mismatch compensator that monitors the output signal to determine the at least one phase offset value, where the at least one phase offset value is utilized by the signal component separator for phase adjustment.
    • 系统和方法可以包括接收非恒定包络输入信号和至少一个相位偏移值的信号分量分离器,并且产生第一数字相位数据和第二数字相位数据; 至少一个数字相位调制器,其接收第一相位数据和第二相位数据,并与频率合成器一起工作,以产生具有第一恒定包络线的第一分量信号和具有第二恒定包络线的第二分量信号; 至少一个放大第一分量信号和第二分量信号的功率放大器; 非隔离功率组合器,其组合所述第一放大分量信号和所述第二放大分量信号以产生具有非常数包络线的输出信号; 以及不匹配补偿器,其监视所述输出信号以确定所述至少一个相位偏移值,其中所述至少一个相位偏移值由所述信号分量分离器用于相位调整。