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1. 发明授权

US08842471B2 Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition 有权
标题翻译：通过在NAND闪存的写操作期间均衡和调节源，阱和位线电平进行充电循环：程序验证转换
公开(公告)号：US08842471B2
公开(公告)日：2014-09-23
申请号：US13570746
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。考虑脉冲和验证阶段之间的间隔。对于脉冲之后的间隔，但是在建立验证条件之前，可以将源极，位线以及可能的阱电平相等化，然后在期望的DC电平进行调节。在验证阶段之后，但是在将存储器应用于下一个脉冲之前，源和位线电平可以均衡为直流电平。

2. 发明申请

US20130176776A1 Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Program to Verify Transition 有权
标题翻译：通过在NAND闪存的写入操作期间均衡和调节源，阱和位线电平进行充电循环：验证转换的程序
公开(公告)号：US20130176776A1
公开(公告)日：2013-07-11
申请号：US13570746
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。考虑脉冲和验证阶段之间的间隔。对于脉冲之后的间隔，但是在建立验证条件之前，可以将源极，位线以及可能的阱电平相等化，然后在期望的DC电平进行调节。在验证阶段之后，但是在将存储器应用于下一个脉冲之前，源和位线电平可以均衡为直流电平。

3. 发明授权

US6140615A Heater apparatus for an aquarium 失效
标题翻译：水族箱加热器
公开(公告)号：US6140615A
公开(公告)日：2000-10-31
申请号：US229963
申请日：1999-01-14
申请人： Masahide Matsumoto
发明人： Masahide Matsumoto
IPC分类号： A01K63/06 , H05B1/02 , H05B3/78 , H05B3/80 , F27D11/00
CPC分类号： H05B1/0283 , A01K63/065 , H05B3/78 , H05B3/80
摘要： A heater apparatus includes a flat-shaped heater portion attachable to a vessel such as a water tank, and a controller for controlling the heater portion. The heater portion includes a flat heater, a first temperature sensor for detecting temperature of the flat heater, and a second temperature sensor for detecting temperature of what is contained in the vessel or water tank. The controller keeps the temperature constant inside the vessel in accordance with the temperature detected by the second temperature sensor. If the rate of rise in temperature detected by the first temperature sensor is faster than is deemed normal, the controller stops current flowing to the flat heater.
摘要翻译：加热器装置包括可连接到诸如水箱的容器的扁平加热器部分和用于控制加热器部分的控制器。加热器部分包括平面加热器，用于检测扁平加热器的温度的第一温度传感器和用于检测容器或水箱中所含的温度的第二温度传感器。控制器根据第二温度传感器检测到的温度保持容器内的温度恒定。如果由第一温度传感器检测到的温度升高速度比正常情况更快，则控制器停止电流流向平面加热器。

4. 发明授权

US5995431A Bit line precharge circuit with reduced standby current 失效
标题翻译：位线预充电电路具有降低的待机电流
公开(公告)号：US5995431A
公开(公告)日：1999-11-30
申请号：US95431
申请日：1998-06-10
申请人： Takashi Inui , Masahide Matsumoto , Kiyotaka Okuzawa
发明人： Takashi Inui , Masahide Matsumoto , Kiyotaka Okuzawa
IPC分类号： G11C7/12 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： A circuit is designed with a memory array (102) having a plurality of memory cells arranged in rows and columns (204, 206, 210, 212). The memory array has a plurality of bit line pairs (202, 208, 282, 284) with each bit line pair connected to a respective column of memory cells and a bit line reference terminal (254). A control circuit (700) produces a control signal, the control signal having a first voltage for a first time, a second voltage for a second time and a third voltage for a third time. A precharge circuit (350, 352) connects at least one bit line pair to the bit line reference terminal, responsive to the first voltage for the first time and the second voltage for the second time. The precharge circuit disconnects the at least one bit line pair from the bit line reference terminal, responsive to the third voltage for the third time.
摘要翻译：电路设计有具有以行和列（204,206,210,212）排列的多个存储单元的存储器阵列（102）。存储器阵列具有多个位线对（202,208,282,284），每个位线对连接到相应的存储单元列和位线参考端（254）。控制电路（700）产生控制信号，该控制信号具有第一次的第一电压，第二次的第二电压和第三次的第三电压。响应于第一次的第一电压和第二次的第二电压，预充电电路（350,352）将至少一个位线对连接到位线参考端。预充电电路响应于第三次的第三电压而断开至少一个位线对与位线参考端子的连接。

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