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1. 发明授权

US06215837B1 Pipe counter signal generator processing double data in semiconductor device 有权
标题翻译：管道计数器信号发生器在半导体器件中处理双数据
公开(公告)号：US06215837B1
公开(公告)日：2001-04-10
申请号：US09471382
申请日：1999-12-22
申请人： Seung-Hyun Yi
发明人： Seung-Hyun Yi
IPC分类号： G11C804
CPC分类号： G11C7/1066 , G11C7/1039 , G11C7/1042 , G11C7/1072 , G11C8/04
摘要： Disclosed is a DDR SDRAM device which may be implemented by simply modifying a pipe counter for an SDR SDRAM device. A pipe counter comprising according to the present invention comprises: a controller for producing a counter control signal in response to rising and falling edge signals of an external clock signal; an enabling unit for producing a plurality of enable signals in response to the counter control signal and for enabling one of the enable signals during one period of the counter control signal; and a driver for receiving one of the enable signals, producing first and second pipe counter signals being synchronized with the rising and falling edge signals of the external clock signal, wherein one of the first and second pipe counter signals is activated during one period of the received enable signal. The DDR SDRAM according to the present invention improves its operation speed without increasing the clock frequency and the bandwidth thereof, by providing the pipe counter controlling data output path.
摘要翻译：公开了一种DDR SDRAM器件，其可以通过简单地修改SDR SDRAM器件的管道计数器来实现。根据本发明的管道计数器包括：控制器，用于响应于外部时钟信号的上升沿和下降沿信号产生计数器控制信号; 启用单元，用于响应于所述计数器控制信号产生多个使能信号，并且用于在所述计数器控制信号的一个周期期间启用所述使能信号中的一个; 以及用于接收使能信号之一的驱动器，产生与外部时钟信号的上升沿和下降沿信号同步的第一和第二管道计数器信号，其中第一和第二管道计数器信号之一在一接收使能信号。根据本发明的DDR SDRAM通过提供管道计数器控制数据输出路径来提高其操作速度而不增加时钟频率及其带宽。

2. 发明授权

US06833744B2 Circuit for correcting duty factor of clock signal 失效
标题翻译：用于校正时钟信号占空比的电路
公开(公告)号：US06833744B2
公开(公告)日：2004-12-21
申请号：US10688685
申请日：2003-10-17
申请人： Seung Hyun Yi
发明人： Seung Hyun Yi
IPC分类号： H03K3017
CPC分类号： H03K5/151 , H03K5/135 , H03K5/1565 , H03K2005/00241 , H03L7/0814
摘要： Circuit for correcting a duty factor of a clock signal, including a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal, a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180° and 360° clock generating control signals, and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180° and 360° clock generating control signals.
摘要翻译：用于校正时钟信号的占空比的电路，包括用于检测具有要校正的占空因数的输入时钟信号的相位差的相位比较器和校正的占空因数的校正时钟信号，并产生移位控制信号控制信号产生部分，用于响应于移位控制信号移位时钟产生参考信号，并延迟时钟产生参考信号预设的时间周期以产生180°和360°的时钟产生控制信号，以及产生时钟信号用于产生具有根据180°和360°时钟产生控制信号的校正占空比的时钟信号的部分。

3. 发明授权

US06314050B1 Data strobe buffer in SDRAM 有权
标题翻译： SDRAM中的数据选通缓冲区
公开(公告)号：US06314050B1
公开(公告)日：2001-11-06
申请号：US09609323
申请日：2000-06-30
申请人： Seung-Hyun Yi , Jong-Hee Han
发明人： Seung-Hyun Yi , Jong-Hee Han
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/1072 , G11C7/22
摘要： A data strobe buffer in SDRAM is disclosed. The data strobe buffer for a synchronous dynamic read only memory (SDRAM), comprising: a first dynamic buffer generating a first pulse at a rising edge of a data strobe signal; a second dynamic buffer generating a second pulse at a falling edge of the data strobe signal; and a block for generating an enable signal which is enabled in a range between a rising edge of an external clock signal and a logic high state of the second pulse, and providing the second dynamic buffer with the enable signal. The data strobe buffer ensures a minimum value of tDQSS parameter in DDR SDRAM even if speed of the chip increases or operation condition of the chip becomes tight, thereby preventing the data strobe buffer from being misoperated due to the damping and the fluctuation of the data strobe signal.
摘要翻译：公开了SDRAM中的数据选通缓冲器。用于同步动态只读存储器（SDRAM）的数据选通缓冲器，包括：第一动态缓冲器，在数据选通信号的上升沿产生第一脉冲; 第二动态缓冲器，在所述数据选通信号的下降沿产生第二脉冲; 以及用于产生使能信号的块，其在外部时钟信号的上升沿和第二脉冲的逻辑高状态之间的范围内被使能，并且向第二动态缓冲器提供使能信号。数据选通缓冲器确保DDR SDRAM中的tDQSS参数的最小值，即使芯片的速度增加或芯片的操作条件变得紧张，从而防止数据选通缓冲区由于阻尼和数据选通的波动而被误操作信号。

4. 发明授权

US5877991A Variable comparison voltage generation apparatus for generating a comparison voltage corresponding to a variation of electric charge quantity in a ferroelectric substance memory element 失效
标题翻译：可变比较电压产生装置，用于产生与铁电物质存储元件中的电荷量变化相对应的比较电压
公开(公告)号：US5877991A
公开(公告)日：1999-03-02
申请号：US057614
申请日：1998-04-08
申请人： Seung Hyun Yi , Jae Hwan Kim
发明人： Seung Hyun Yi , Jae Hwan Kim
IPC分类号： G11C14/00 , G11C5/14 , G11C7/14 , G11C11/22 , G11C29/38 , G11C29/50 , G11C16/04
CPC分类号： G11C29/38 , G11C11/22 , G11C29/50 , G11C5/147 , G11C7/14 , G11C2029/5004
摘要： A variable comparison voltage generation apparatus for a semiconductor memory element substitutes a variable comparison voltage amplifier for a fixed comparison voltage amplifier used for a ferroelectric substance memory. The variable comparison voltage generation apparatus according to the present invention accurately detect the data stored in the memory element with ferroelectric substance.
摘要翻译：用于半导体存储元件的可变比较电压产生装置用可变比较电压放大器代替用于铁电物质存储器的固定比较电压放大器。根据本发明的可变比较电压产生装置用铁电物质精确地检测存储在存储元件中的数据。

5. 发明授权

US06356502B1 Address strobe signal generator for memory device 失效
标题翻译：地址选通信号发生器用于存储器件
公开(公告)号：US06356502B1
公开(公告)日：2002-03-12
申请号：US09428131
申请日：1999-10-26
申请人： Seung-Hyun Yi
发明人： Seung-Hyun Yi
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C5/06
摘要： An apparatus and method for decoding address signals. The apparatus generally comprises an address buffer array, a buffer controller coupled to the address buffer array, an address decoder coupled to the address buffer array and a strobe generator coupled to the address decoder and the buffer controller. The address buffer array buffers address signals in response to an address strobe from the buffer controller. The strobe generator generates a decoding strobe in response to the address strobe. The decoding strobe signals the address decoder to decode the address signals received from the address buffer array. To synchronize the arrival of the decoding strobe and the buffered address signals at the decoder, the strobe generator has one or more signal transfer characteristics in common with one or more of the address buffers. In a specific embodiment, the strobe generator has a longer signal transfer delay than any address buffer in the address buffer array. Thus, the decoding strobe determines an input timing margin of the address decoder.
摘要翻译：一种用于解码地址信号的装置和方法。该装置通常包括地址缓冲器阵列，耦合到地址缓冲器阵列的缓冲器控制器，耦合到地址缓冲器阵列的地址解码器和耦合到地址解码器和缓冲器控制器的选通发生器。响应于来自缓冲器控制器的地址选通，地址缓冲器阵列缓冲地址信号。选通发生器响应于地址选通器产生解码选通。解码选通信号通知地址解码器以解码从地址缓冲器阵列接收的地址信号。为了在解码器处同步解码选通和缓冲的地址信号的到来，选通发生器具有与一个或多个地址缓冲器相同的一个或多个信号传送特性。在具体实施例中，选通发生器具有比地址缓冲器阵列中的任何地址缓冲器更长的信号传输延迟。因此，解码选通器确定地址解码器的输入定时裕度。

6. 发明授权

US6041005A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6041005A
公开(公告)日：2000-03-21
申请号：US342105
申请日：1999-06-29
申请人： Seung Hyun Yi , Jae Whan Kim
发明人： Seung Hyun Yi , Jae Whan Kim
IPC分类号： G11C11/407 , G11C11/22 , G11C11/4074 , G11C13/00
CPC分类号： G11C11/4074 , G11C11/22
摘要： The present invention relates to semiconductor memory device and more particularly, to a technique for stabilizing the potential of the cell plate line by using two kinds of potentials for the cell plate line driver to implement the powerful driving force and rapid operability required in case of designing the RAM using as the memory device the material having large electrostatic capacity, and for preventing the loss of I/O by using CMOS transistors in the decoder circuit which receives the cell plate line voltage by cooperating with the cell plate line driver circuit and feeds back the cell plate line voltage.
摘要翻译：本发明涉及半导体存储器件，更具体地，涉及通过使用两种电池板线驱动器的电位来稳定电池板线的电位的技术，以实现强大的驱动力和在设计的情况下所需的快速可操作性该RAM使用具有大静电容量的材料作为存储器件，并且通过在解码器电路中使用CMOS晶体管来防止I / O的损失，该解码器电路通过与单元板线驱动电路配合并反馈来接收单元板线电压细胞板线电压。

7. 发明授权

US06933755B2 Output driving circuit for maintaining I/O signal duty ratios 失效
标题翻译：用于保持I / O信号占空比的输出驱动电路
公开(公告)号：US06933755B2
公开(公告)日：2005-08-23
申请号：US10688607
申请日：2003-10-17
申请人： Kuk Tae Hong , Seung Hyun Yi
发明人： Kuk Tae Hong , Seung Hyun Yi
IPC分类号： G11C7/10 , H03K19/003 , H03K19/0185 , H03K3/00
CPC分类号： G11C7/1057 , G11C7/1051 , H03K19/00323 , H03K19/018521
摘要： Output driving circuit including at least one or more than one level shifter for receiving an input signal to be provided to an outside of an integrated circuit and shifting a voltage level of the input signal to a voltage level required at the outside of the integrated circuit while maintaining a duty ratio of the input signal constant, and an output driving unit for forwarding the input signal to the outside of the integrated circuit under the control of an output enable signal, thereby permitting application to the integrated circuit operative at a high speed, readily.
摘要翻译：输出驱动电路包括至少一个或多于一个电平移位器，用于接收要提供给集成电路外部的输入信号，并将输入信号的电压电平移位到集成电路外部所需的电压电平，同时保持输入信号的占空比恒定;以及输出驱动单元，用于在输出使能信号的控制下将输入信号转发到集成电路的外部，从而允许应用到高速运行的集成电路。

8. 发明授权

US06708255B2 Variable input/output control device in synchronous semiconductor device 有权
标题翻译：同步半导体器件中可变输入/输出控制器件
公开(公告)号：US06708255B2
公开(公告)日：2004-03-16
申请号：US10029948
申请日：2001-12-31
申请人： Seung-Hyun Yi
发明人： Seung-Hyun Yi
IPC分类号： G06F1200
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C2207/107
摘要： A variable input/output control device in a synchronous semiconductor memory device including a plurality of first prefetch units to prefetch data from an input buffer, a plurality of second prefetch units to prefetch data from a memory core and a control signal generator for generating a control signal in response to command signals to select one of the plurality of first prefetch units and one of the plurality of second prefetch units.
摘要翻译：一种同步半导体存储装置中的可变输入/输出控制装置，包括从输入缓冲器预取数据的多个第一预取单元，用于从存储器内核预取数据的多个第二预取单元和用于产生控制的控制信号发生器响应于命令信号来选择所述多个第一预取单元中的一个和所述多个第二预取单元中的一个。

9. 发明授权

US6101119A Apparatus for driving cell plate line of memory device using two power supply voltage sources 有权
标题翻译：用于使用两个电源电压源驱动存储器件的单元板线的装置
公开(公告)号：US6101119A
公开(公告)日：2000-08-08
申请号：US428547
申请日：1999-10-28
申请人： Seung-Hyun Yi , Jae-Whan Kim
发明人： Seung-Hyun Yi , Jae-Whan Kim
IPC分类号： G11C11/407 , G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： An apparatus for driving a cell plate line of a semiconductor memory device having a plurality of memory cells, includes: a first driving means for driving the cell plate line with a first power supply voltage; a second driving means for driving the cell plate line with a second power supply voltage higher than the first power supply voltage; and a driving control means for enabling said second driving means for a predetermined time in order to activate the cell plate line in response to a control signal from an external circuit and enabling said first driving means after the predetermined time in order to stabilize said second driving means enables, wherein the control signal is employed to select one memory cell related to the cell plate line. Thereby, the apparatus can the high-speed operation of a ferroelectric random access memory (FeRAM) by using two power supply voltage sources.
摘要翻译：一种用于驱动具有多个存储单元的半导体存储器件的单元板线的装置，包括：用于以第一电源电压驱动单元板线的第一驱动装置; 第二驱动装置，用于以高于第一电源电压的第二电源电压驱动单元板板线; 以及驱动控制装置，用于使所述第二驱动装置能够预定的时间，以便响应于来自外部电路的控制信号激活所述单元板线，并且在所述预定时间之后启用所述第一驱动装置，以便稳定所述第二驱动装置使能，其中所述控制信号用于选择与所述细胞板线有关的一个存储单元。因此，该装置可以通过使用两个电源电压源来高速运行铁电随机存取存储器（FeRAM）。

10. 发明授权

US06625067B2 Semiconductor memory device for variably controlling drivability 有权
公开(公告)号：US06625067B2
公开(公告)日：2003-09-23
申请号：US10029947
申请日：2001-12-31
申请人： Seung-Hyun Yi
发明人： Seung-Hyun Yi
IPC分类号： G11C1604
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C8/12
摘要： A semiconductor memory device including an N-bit prefetch unit, a plurality of data output drivers to output data from the N-bit prefetch unit and a control signal generator for generating a plurality of control signals in response to command signals, wherein the plurality of data output drivers are driven by the control signals.

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