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1. 发明授权

US5723889A Semiconductor memory device and method for fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5723889A
公开(公告)日：1998-03-03
申请号：US520435
申请日：1995-08-29
申请人： Jong Mun Choi , Chang Yeol Kim , Woun-Suck Yang
发明人： Jong Mun Choi , Chang Yeol Kim , Woun-Suck Yang
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L21/465
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A semiconductor memory device includes a semiconductor substrate, a first insulation film formed on the substrate, a trench formed in the substrate, an opening formed in the first insulation film above the trench, a capacitor including a dielectric film formed in the trench and a storage node formed in the trench on the dielectric film, a transfer transistor including a channel layer formed in the opening on the storage node, a gate insulation film formed on the channel layer, and a gate electrode formed on the gate insulation film, a second insulation film formed on the gate electrode, a conduction layer formed on the second insulation film, a third insulation film in contact with the channel layer, and a bit line in contact with the conduction layer.
摘要翻译：半导体存储器件包括半导体衬底，形成在衬底上的第一绝缘膜，在衬底中形成的沟槽，形成在沟槽上方的第一绝缘膜中的开口，包括形成在沟槽中的电介质膜的电容器和存储器形成在电介质膜上的沟槽中的传输晶体管，包括形成在存储节点上的开口中的沟道层的传输晶体管，形成在沟道层上的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极，第二绝缘层形成在栅电极上的膜，形成在第二绝缘膜上的导电层，与沟道层接触的第三绝缘膜，以及与导电层接触的位线。

2. 发明申请

US20050208715A1 Method of fabricating fin field effect transistor using isotropic etching technique 有权
标题翻译：使用各向同性蚀刻技术制造散射场效应晶体管的方法
公开(公告)号：US20050208715A1
公开(公告)日：2005-09-22
申请号：US11083660
申请日：2005-03-16
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
CPC分类号： H01L29/7851 , H01L29/66818
摘要： Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.
摘要翻译：公开了制造鳍式场效应晶体管（FinFET）的方法。本发明的实施例提供了通过优化用于形成翅片的方法来制造FinFET的方法，使得防止短通道效应并实现高集成度。因此，可以容易地形成使用当前的光刻蚀刻技术难以形成的翅片。

3. 发明申请

US20050179030A1 Field effect transistor device with channel fin structure and method of fabricating the same 失效
标题翻译：具有通道鳍结构的场效应晶体管器件及其制造方法
公开(公告)号：US20050179030A1
公开(公告)日：2005-08-18
申请号：US10938436
申请日：2004-09-09
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66795
摘要： A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.
摘要翻译： finFET器件包括具有被沟槽包围的特定区域的半导体衬底。沟槽填充有绝缘层，并且在特定区域内形成凹陷孔，使得通道散热片由凹槽两侧的半导体衬底的凸起部分形成。栅极线形成为覆盖并延伸穿过通道散热片。源极/漏极区域形成在通道鳍片的两端并且通过通道散热片连接。描述和要求保护其他实施例。

4. 发明申请

US20080185641A1 Recessed transistor and method of manufacturing the same 有权
标题翻译：嵌入式晶体管及其制造方法
公开(公告)号：US20080185641A1
公开(公告)日：2008-08-07
申请号：US12068179
申请日：2008-02-04
申请人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
发明人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
摘要翻译：提供凹陷晶体管及其制造方法。凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。衬底可以包括建立衬底的有源区和场区的隔离层。衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。源/漏区可以与有源区和栅电极相邻形成。

5. 发明授权

US09012982B2 Recessed transistor and method of manufacturing the same 有权
标题翻译：嵌入式晶体管及其制造方法
公开(公告)号：US09012982B2
公开(公告)日：2015-04-21
申请号：US12068179
申请日：2008-02-04
申请人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
发明人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
摘要翻译：提供凹陷晶体管及其制造方法。凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。衬底可以包括建立衬底的有源区和场区的隔离层。衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。源/漏区可以与有源区和栅电极相邻形成。

6. 发明授权

US07393769B2 Transistor of a semiconductor device having a punchthrough protection layer and methods of forming the same 有权
标题翻译：具有穿透保护层的半导体器件的晶体管及其形成方法
公开(公告)号：US07393769B2
公开(公告)日：2008-07-01
申请号：US11077835
申请日：2005-03-10
申请人： Hyeoung-Won Seo , Ki-Nam Kim , Woun-Suck Yang , Du-Heon Song
发明人： Hyeoung-Won Seo , Ki-Nam Kim , Woun-Suck Yang , Du-Heon Song
IPC分类号： H01L29/40
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10861 , H01L29/1083
摘要： According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line pattern fills an upper portion of the channel-portion hole, and is formed on the semiconductor substrate. The word line pattern is formed to have a word line and a word line capping layer pattern stacked thereon, and the channel-portion layer is a channel region. The punchthrough protection layer can reduce a leakage current of a capacitor of the transistor embodied in a DRAM.
摘要翻译：根据本发明的一些实施例，半导体器件的晶体管具有穿透保护层，并且提供了其形成方法。沟道部分孔从半导体衬底的主表面向下延伸。穿通保护层和沟道部分层依次形成在沟道部分孔的下部。字线图案填充沟道部分孔的上部，并形成在半导体衬底上。字线图案形成为具有堆叠在其上的字线和字线覆盖层图案，并且沟道部分层是沟道区域。穿透保护层可以减少体现在DRAM中的晶体管的电容器的漏电流。

7. 发明授权

US07279774B2 Bulk substrates in FinFETs with trench insulation surrounding FIN pairs having FINs separated by recess hole shallower than trench 失效
标题翻译： FinFET中的散装衬底，具有沟槽绝缘体，其周围具有FIN对，其具有通过比沟槽浅的凹槽分隔的FIN
公开(公告)号：US07279774B2
公开(公告)日：2007-10-09
申请号：US10938436
申请日：2004-09-09
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Youn
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Youn
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/785 , H01L29/66795
摘要： A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.
摘要翻译： finFET器件包括具有被沟槽包围的特定区域的半导体衬底。沟槽填充有绝缘层，并且在特定区域内形成凹陷孔，使得通道散热片由凹槽两侧的半导体衬底的凸起部分形成。栅极线形成为覆盖并延伸穿过通道散热片。源极/漏极区域形成在通道鳍片的两端并且通过通道散热片连接。描述和要求保护其他实施例。

8. 发明授权

US07429505B2 Method of fabricating fin field effect transistor using isotropic etching technique 有权
标题翻译：使用各向同性蚀刻技术制造散射场效应晶体管的方法
公开(公告)号：US07429505B2
公开(公告)日：2008-09-30
申请号：US11560768
申请日：2006-11-16
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/331
CPC分类号： H01L29/7851 , H01L29/66818
摘要： Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.
摘要翻译：公开了制造鳍式场效应晶体管（FinFET）的方法。本发明的实施例提供了通过优化用于形成翅片的方法来制造FinFET的方法，使得防止短通道效应并实现高集成度。因此，可以容易地形成使用当前的光刻蚀刻技术难以形成的翅片。

9. 发明申请

US20080084731A1 DRAM devices including fin transistors and methods of operating the DRAM devices 审中-公开
标题翻译：包括鳍式晶体管的DRAM器件和操作DRAM器件的方法
公开(公告)号：US20080084731A1
公开(公告)日：2008-04-10
申请号：US11896029
申请日：2007-08-29
申请人： Chul Lee , Dong-Gun Park , Woun-Suck Yang , Makoto Yoshida
发明人： Chul Lee , Dong-Gun Park , Woun-Suck Yang , Makoto Yoshida
IPC分类号： G11C11/401 , H01L27/108
CPC分类号： G11C11/404 , G11C11/4076 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L27/10894 , H01L29/7851
摘要： A dynamic random access memory (DRAM) device may include: a semiconductor substrate including an active fin, an active region, and an isolation layer; one or more cell gate structures on a central portion of the active fin; one or more dummy gate structures on a peripheral portion of the active fin; one or more source/drain regions at an upper portion of the active fin adjacent to the one or more cell gate structures; a first insulating interlayer on the semiconductor substrate; a bit line structure electrically connected to the at least one source region; a second insulating interlayer on the first insulating interlayer; one or more capacitors electrically connected to the at least one drain region; a third insulating interlayer on the second insulating interlayer; and a wire connected to the active region and at least one of the one or more dummy gate structures.
摘要翻译：动态随机存取存储器（DRAM）装置可以包括：半导体衬底，其包括有源鳍片，有源区域和隔离层; 有源鳍片的中心部分上的一个或多个单元栅极结构; 活动鳍片的周边部分上的一个或多个虚拟栅极结构; 在与所述一个或多个单元栅极结构相邻的所述有源鳍片的上部处的一个或多个源极/漏极区域; 半导体衬底上的第一绝缘中间层; 电连接到所述至少一个源极区的位线结构; 在所述第一绝缘中间层上的第二绝缘中间层; 电连接到所述至少一个漏极区的一个或多个电容器; 在所述第二绝缘中间层上的第三绝缘中间层; 以及连接到有源区域和所述一个或多个虚拟栅极结构中的至少一个的导线。

10. 发明授权

US07153733B2 Method of fabricating fin field effect transistor using isotropic etching technique 有权
标题翻译：使用各向同性蚀刻技术制造散射场效应晶体管的方法
公开(公告)号：US07153733B2
公开(公告)日：2006-12-26
申请号：US11083660
申请日：2005-03-16
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/331
CPC分类号： H01L29/7851 , H01L29/66818
摘要： Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.
摘要翻译：公开了制造鳍式场效应晶体管（FinFET）的方法。本发明的实施例提供了通过优化用于形成翅片的方法来制造FinFET的方法，使得防止短通道效应并实现高集成度。因此，可以容易地形成使用当前的光刻蚀刻技术难以形成的翅片。

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