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1. 发明申请

US20080185641A1 Recessed transistor and method of manufacturing the same 有权
标题翻译：嵌入式晶体管及其制造方法
公开(公告)号：US20080185641A1
公开(公告)日：2008-08-07
申请号：US12068179
申请日：2008-02-04
申请人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
发明人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
摘要翻译：提供凹陷晶体管及其制造方法。凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。衬底可以包括建立衬底的有源区和场区的隔离层。衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。源/漏区可以与有源区和栅电极相邻形成。

2. 发明授权

US09012982B2 Recessed transistor and method of manufacturing the same 有权
标题翻译：嵌入式晶体管及其制造方法
公开(公告)号：US09012982B2
公开(公告)日：2015-04-21
申请号：US12068179
申请日：2008-02-04
申请人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
发明人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
摘要翻译：提供凹陷晶体管及其制造方法。凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。衬底可以包括建立衬底的有源区和场区的隔离层。衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。源/漏区可以与有源区和栅电极相邻形成。

3. 发明申请

US20080084731A1 DRAM devices including fin transistors and methods of operating the DRAM devices 审中-公开
标题翻译：包括鳍式晶体管的DRAM器件和操作DRAM器件的方法
公开(公告)号：US20080084731A1
公开(公告)日：2008-04-10
申请号：US11896029
申请日：2007-08-29
申请人： Chul Lee , Dong-Gun Park , Woun-Suck Yang , Makoto Yoshida
发明人： Chul Lee , Dong-Gun Park , Woun-Suck Yang , Makoto Yoshida
IPC分类号： G11C11/401 , H01L27/108
CPC分类号： G11C11/404 , G11C11/4076 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L27/10894 , H01L29/7851
摘要： A dynamic random access memory (DRAM) device may include: a semiconductor substrate including an active fin, an active region, and an isolation layer; one or more cell gate structures on a central portion of the active fin; one or more dummy gate structures on a peripheral portion of the active fin; one or more source/drain regions at an upper portion of the active fin adjacent to the one or more cell gate structures; a first insulating interlayer on the semiconductor substrate; a bit line structure electrically connected to the at least one source region; a second insulating interlayer on the first insulating interlayer; one or more capacitors electrically connected to the at least one drain region; a third insulating interlayer on the second insulating interlayer; and a wire connected to the active region and at least one of the one or more dummy gate structures.
摘要翻译：动态随机存取存储器（DRAM）装置可以包括：半导体衬底，其包括有源鳍片，有源区域和隔离层; 有源鳍片的中心部分上的一个或多个单元栅极结构; 活动鳍片的周边部分上的一个或多个虚拟栅极结构; 在与所述一个或多个单元栅极结构相邻的所述有源鳍片的上部处的一个或多个源极/漏极区域; 半导体衬底上的第一绝缘中间层; 电连接到所述至少一个源极区的位线结构; 在所述第一绝缘中间层上的第二绝缘中间层; 电连接到所述至少一个漏极区的一个或多个电容器; 在所述第二绝缘中间层上的第三绝缘中间层; 以及连接到有源区域和所述一个或多个虚拟栅极结构中的至少一个的导线。

4. 发明申请

US20050184348A1 Semiconductor device gate structure and method of forming the same 审中-公开
标题翻译：半导体器件栅极结构及其形成方法
公开(公告)号：US20050184348A1
公开(公告)日：2005-08-25
申请号：US11059145
申请日：2005-02-15
申请人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
发明人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L21/823487 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78618 , H01L29/78642
摘要： A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, and a first conductive pattern extends from a lower portion of the channel pattern in a first direction verticalperpendicular to the channel pattern and in parallel with the substrate. A second conductive pattern extends from an upper portion of the channel pattern in a second direction verticalperpendicular to the channel pattern and in parallel with the substrate. Accordingly, the channel length of the MOS transistor is determined by a distance between the first and second conductive patterns, and a channel width of the MOS transistor is determined by a diameter of the gate structure. Short channel and narrow width effects are sufficiently prevented in a MOS transistor.
摘要翻译：公开了一种MOS晶体管，其包括在垂直方向上延伸半导体衬底的栅极结构。栅极结构包括从垂直方向从衬底延伸的栅极电极和围绕栅电极的栅极绝缘层。沟道图案包围栅极绝缘层，并且第一导电图案沿着垂直于沟道图案的第一方向并且与衬底平行地从沟道图案的下部延伸。第二导电图案沿着垂直于沟道图案的第二方向并与衬底平行地从沟道图案的上部延伸。因此，MOS晶体管的沟道长度由第一和第二导电图案之间的距离决定，并且MOS晶体管的沟道宽度由栅极结构的直径决定。在MOS晶体管中充分防止了短沟道和窄宽度效应。

5. 发明授权

US07919378B2 Transistor and method of forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US07919378B2
公开(公告)日：2011-04-05
申请号：US12397176
申请日：2009-03-03
申请人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
发明人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
摘要翻译：根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。活性结构包括在源极/漏极区域下形成阻挡区的沟槽。栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

6. 发明申请

US20050176186A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050176186A1
公开(公告)日：2005-08-11
申请号：US11048369
申请日：2005-01-31
申请人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
发明人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/785 , H01L29/7854 , H01L29/78603 , H01L29/78648
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.
摘要翻译：在一个实施例中，半导体器件包括具有下层和覆盖在下层上的上层的半导体衬底。上层被布置和构造成形成彼此间隔开并从下层的上表面突出的第一和第二有源区。桥接形状的第三有源区域与下层的上表面垂直地间隔开并且连接第一和第二有源区域。该器件还包括栅电极，其形成有围绕第三有源区的栅绝缘层，使得第三有源区用作沟道。

7. 发明授权

US07323375B2 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US07323375B2
公开(公告)日：2008-01-29
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

8. 发明申请

US20050250285A1 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US20050250285A1
公开(公告)日：2005-11-10
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L29/786 , H01L29/94
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

9. 发明授权

US07579648B2 Semiconductor device having a channel pattern and method of manufacturing the same 有权
标题翻译：具有沟道图案的半导体器件及其制造方法
公开(公告)号：US07579648B2
公开(公告)日：2009-08-25
申请号：US11183997
申请日：2005-07-19
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/78696 , H01L29/66666 , H01L29/66772 , H01L29/78642
摘要： A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive region, which may serve as lower source/drain regions, may be formed at a surface portion of the semiconductor substrate. The conductive region may contact a lower portion of the channel pattern. A conductive pattern, which may serve as upper source/drain regions, may horizontally extend from an upper portion of the channel pattern.
摘要翻译：半导体器件可以包括从半导体衬底垂直延伸的管状沟道图案。可以在通过通道图案暴露的面上设置栅极绝缘层。栅极电极可以设置在栅极绝缘层上。栅电极可以填充沟道图案。可以在半导体衬底的表面部分处形成可用作下部源极/漏极区域的导电区域。导电区域可以接触通道图案的下部。可以用作上部源极/漏极区域的导电图案可以从沟道图案的上部部分水平延伸。

10. 发明申请

US20080293203A1 Semiconductor device having a fin structure and method of manufacturing the same 失效
标题翻译：具有翅片结构的半导体器件及其制造方法
公开(公告)号：US20080293203A1
公开(公告)日：2008-11-27
申请号：US12219984
申请日：2008-07-31
申请人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
发明人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.
摘要翻译：半导体器件可以包括具有连接在源极/漏极图案之间的源极/漏极区域和沟道鳍片的鳍结构。栅极绝缘层可以设置在通道散热片上。栅电极可以包括下栅极图案和上栅极图案。下栅极图案可以在垂直方向上延伸并接触栅极绝缘层。上栅极图案可以在基本上垂直于第一水平方向的第二水平方向上延伸。上栅极图案可以连接到下栅极图案的上部。

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