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1. 发明申请

US20110173584A1 REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION 有权
标题翻译：通过锁定极性反转来减少逻辑和延迟
公开(公告)号：US20110173584A1
公开(公告)日：2011-07-14
申请号：US12685803
申请日：2010-01-12
申请人： Jonathan Y. Chen , Jose L. Neves
发明人： Jonathan Y. Chen , Jose L. Neves
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist.
摘要翻译：一种用于减少逻辑结构内的逻辑和延迟的方法，包括搜索待分析的逻辑结构，在要分析的逻辑结构内找到多个锁存器，确定多个锁存器中的任何相应的锁存器是否在输入内具有足够的正的松弛并且可选地排除相应的锁存器的分析，确定是否存在至少一个待分析的剩余锁存器，以及确定逆变器是否设置在所述至少一个剩余锁存器的输入路径和输出路径内。该方法还包括：当发现逆变器时获得至少一个剩余锁存器的输入路径和输出路径的逻辑功能，使用DeMorgan's定理修改逻辑功能，确定定时违反是否存在于修改后的逻辑功能上，以及注释硬件描述语言基于修改的逻辑功能，当没有定时违反时。

2. 发明授权

US08108821B2 Reduction of logic and delay through latch polarity inversion 有权
标题翻译：通过锁存极性反转减少逻辑和延迟
公开(公告)号：US08108821B2
公开(公告)日：2012-01-31
申请号：US12685803
申请日：2010-01-12
申请人： Jonathan Y. Chen , Jose L. Neves
发明人： Jonathan Y. Chen , Jose L. Neves
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist.
摘要翻译：一种用于减少逻辑结构内的逻辑和延迟的方法，包括搜索待分析的逻辑结构，在要分析的逻辑结构内找到多个锁存器，确定多个锁存器中的任何相应的锁存器是否在输入内具有足够的正的松弛并且可选地排除相应的锁存器的分析，确定是否存在至少一个待分析的剩余锁存器，以及确定逆变器是否设置在所述至少一个剩余锁存器的输入路径和输出路径内。该方法还包括：当发现逆变器时获得至少一个剩余锁存器的输入路径和输出路径的逻辑功能，使用DeMorgan's定理修改逻辑功能，确定定时违反是否存在于修改后的逻辑功能上，以及注释硬件描述语言基于修改的逻辑功能，当没有定时违反时。

3. 发明授权

US07831946B2 Clock distribution network wiring structure 有权
标题翻译：时钟分配网络布线结构
公开(公告)号：US07831946B2
公开(公告)日：2010-11-09
申请号：US11830910
申请日：2007-07-31
申请人： Rick L. Dennis , Charlie C. Hwang , Jose L. Neves
发明人： Rick L. Dennis , Charlie C. Hwang , Jose L. Neves
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.
摘要翻译：用于时钟信号的布线结构具有布置在相邻电源线托架中的两个或更多个并联时钟信号线，其跨越时钟信号线将耦合到的汇点之间的距离。并行时钟信号线通过放置在位置处的短截线彼此短路，以便时钟布线结构。结构的延迟调谐通过预定义电网的布线槽之间的布线短路的离散运动来获得。

4. 发明授权

US07823108B2 Chip having timing analysis of paths performed within the chip during the design process 有权
标题翻译：芯片具有在设计过程中在芯片内执行的路径的定时分析
公开(公告)号：US07823108B2
公开(公告)日：2010-10-26
申请号：US11934995
申请日：2007-11-05
申请人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. Mcllvain , Jose L. Neves , Ray Raphy , Douglas S. Search
发明人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. Mcllvain , Jose L. Neves , Ray Raphy , Douglas S. Search
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5031
摘要： An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
摘要翻译：使用Genie制造的集成电路芯片，Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。具体来说，Genie团体失败了进入时代岛的路径。定时岛是包含至少一个共享段的一组路径。最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。将定时岛作为一棵树，岛上的中心将是树干。如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

5. 发明申请

US20090033398A1 Clock Distribution Network Wiring Structure 有权
标题翻译：时钟分配网络接线结构
公开(公告)号：US20090033398A1
公开(公告)日：2009-02-05
申请号：US11830910
申请日：2007-07-31
申请人： Rick L. Dennis , Charlie C. Hwang , Jose L. Neves
发明人： Rick L. Dennis , Charlie C. Hwang , Jose L. Neves
IPC分类号： G06F1/04 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.
摘要翻译：用于时钟信号的布线结构具有布置在相邻电源线托架中的两个或更多个并联时钟信号线，其跨越时钟信号线将耦合到的汇点之间的距离。并行时钟信号线通过放置在位置处的短截线彼此短路，以便时钟布线结构。结构的延迟调谐通过预定义电网的布线槽之间的布线短路的离散运动来获得。

6. 发明授权

US07356793B2 Genie: a method for classification and graphical display of negative slack timing test failures 有权
标题翻译： Genie：用于分类和图形显示负松弛时序测试故障的方法
公开(公告)号：US07356793B2
公开(公告)日：2008-04-08
申请号：US11129784
申请日：2005-05-16
申请人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. McIlvain , Jose L. Neves , Ray Raphy , Douglas S. Search
发明人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. McIlvain , Jose L. Neves , Ray Raphy , Douglas S. Search
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
摘要翻译： Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。具体来说，Genie团体失败了进入时代岛的路径。定时岛是包含至少一个共享段的一组路径。最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。将定时岛作为一棵树，岛上的中心将是树干。如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

7. 发明授权

US09223918B2 Reducing repeater power 有权
标题翻译：减少中继器功率
公开(公告)号：US09223918B2
公开(公告)日：2015-12-29
申请号：US13447751
申请日：2012-04-16
申请人： Paul D. Kartschoke , Adam P. Matheny , Jose L. Neves
发明人： Paul D. Kartschoke , Adam P. Matheny , Jose L. Neves
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5036
摘要： A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.
摘要翻译：提供了一种用于减少中继器功率和串扰的方法，系统和计算机可读介质。该方法包括生成包括连接在至少一个源和至少一个宿之间的多个原始中继器的电路的模型，对多个原始中继器执行功率优化分析以将多个原始中继器改变为低功率中继器基于预定的优化参数，对包括低功率中继器的电路的模型执行串扰分析，以确定是否存在串扰定时违反，以及当至少一个低功率中继器改变为较高功率中继器时确定存在串扰冲突，并且当确定不存在串扰冲突时，将低功率中继器留在电路模型中。

8. 发明授权

US07921398B2 System and medium for placement which maintain optimized timing behavior, while improving wireability potential 有权
标题翻译：用于放置的系统和介质，其保持优化的定时行为，同时提高可线性潜力
公开(公告)号：US07921398B2
公开(公告)日：2011-04-05
申请号：US12047382
申请日：2008-03-13
申请人： James J. Curtin , Jose L. Neves , Douglas S. Search
发明人： James J. Curtin , Jose L. Neves , Douglas S. Search
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5031 , G06F17/5072 , G06F2217/84
摘要： A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.
摘要翻译：提出了一种确定集成电路设计过程中电路布局的方法。该方法包括访问识别电路连接的网络列表。在网络列表内的定时路径中将多个单独的净权重分配给网络。对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。与此同时，利用我们的新的同时进行的改进方法是有利的，以通过额外的时序优化和净重映射修改步骤来改善所述设计的可线性。

9. 发明授权

US07810062B2 Method for eliminating negative slack in a netlist via transformation and slack categorization 有权
标题翻译：通过转换和松散分类消除网表中的负松弛的方法
公开(公告)号：US07810062B2
公开(公告)日：2010-10-05
申请号：US11853573
申请日：2007-09-11
申请人： James J. Curtin , William E. Dougherty, Jr. , Jose L. Neves , Douglas S. Search
发明人： James J. Curtin , William E. Dougherty, Jr. , Jose L. Neves , Douglas S. Search
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
摘要翻译：用于消除表示芯片设计的网表中的负松弛的方法使用设计的定时环境来在逻辑和物理合成阶段将信息叠加到设计环境上。重叠的定时信息确定哪个网表转换为负消除消除提供了最大的杠杆作用，以及为每个设计调整的创建动态变换配方的方法。该方法进一步提供消极消除的上限，以防止网表变换被应用于超出改进设计能力的情况。

10. 发明申请

US20080163149A1 System and Medium for Placement Which Maintain Optimized Timing Behavior, While Improving Wireability Potential 有权
标题翻译：系统和介质放置，保持优化的时序行为，同时提高可接线性潜力
公开(公告)号：US20080163149A1
公开(公告)日：2008-07-03
申请号：US12047382
申请日：2008-03-13
申请人： James J. Curtin , Jose L. Neves , Douglas S. Search
发明人： James J. Curtin , Jose L. Neves , Douglas S. Search
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5072 , G06F2217/84
摘要： A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.
摘要翻译：提出了一种确定集成电路设计过程中电路布局的方法。该方法包括访问识别电路连接的网络列表。在网络列表内的定时路径中将多个单独的净权重分配给网络。对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。与此同时，利用我们的新的同时进行的改进方法是有利的，以通过附加的时序优化和净重映射修改步骤来提高所述设计的可线性。

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