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1. 发明授权

US06853509B2 Acquisition signal error estimator 有权
标题翻译：采集信号误差估计器
公开(公告)号：US06853509B2
公开(公告)日：2005-02-08
申请号：US10322243
申请日：2002-12-17
申请人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
发明人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
IPC分类号： G11B5/09 , G11B20/10 , G11B20/22
CPC分类号： G11B20/10037 , G11B5/09 , G11B20/10009 , G11B20/10055 , G11B20/22
摘要： A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample value without comparing the received sample value to the potential sample values. According to one embodiment, the nearest ideal sample value is selected based on the received sample value and values of three consecutive samples. According to another embodiment, the nearest ideal sample value is selected based on the received sample value and a value of an immediately preceding sample. According yet to another embodiment, the nearest ideal sample value is selected based on the received sample value and a value of a previous sample. The acquisition signal error estimator maybe used in conjunction with gain, DC offset, or magneto-resistive asymmetry control loops in a sampled amplitude read channel.
摘要翻译：提供了一种用于采集信号误差估计的系统和方法，其使用该序列的一个或多个过去值来确定最接近的理想采样值，而不将接收到的采样值与潜在采样值相比较。根据一个实施例，基于接收到的采样值和三个连续样本的值来选择最接近的理想采样值。根据另一个实施例，基于所接收的采样值和紧接在前的样本的值来选择最接近的理想采样值。根据另一个实施例，基于所接收的采样值和先前样本的值来选择最接近的理想采样值。采集信号误差估计器可以与采样幅度读通道中的增益，直流偏移或磁阻不对称控制环路结合使用。

2. 发明授权

US06594094B2 Read/write channel 有权
标题翻译：读/写通道
公开(公告)号：US06594094B2
公开(公告)日：2003-07-15
申请号：US10025001
申请日：2001-12-18
申请人： James W. Rae , William Bliss , Jonathan Ashley , Razmik Karabed , Stephen J. Franck , Fritz Mistlberger , Matthias Driller , Heinrich Stockmanns , Dominik Margraf
发明人： James W. Rae , William Bliss , Jonathan Ashley , Razmik Karabed , Stephen J. Franck , Fritz Mistlberger , Matthias Driller , Heinrich Stockmanns , Dominik Margraf
IPC分类号： G11B502
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B5/59688 , G11B5/6076 , G11B20/10009 , G11B20/10037
摘要： An improved sampled amplitude read/write channel is provided. The system is an integrated Generalized Partial Response Maximum Likelihood (GPRML) read channel incorporating Read, Write, and Servo modes of operation. One implementation includes a 32/34 rate parity code and matched Viterbi detector, a 32 state Viterbi detector optimal parity processor, robust frame synchronization, self-adaptive equalization, thermal asperity detection and compensation, adaptive magneto-resistive asymmetry compensation, low latency interpolated timing recovery and programmable write precompensation.
摘要翻译：提供了一种改进的采样幅度读/写通道。该系统是集成了读，写和伺服操作模式的集成广义部分响应最大似然（GPRML）读通道。一个实现包括32/34速率奇偶校验码和匹配维特比检测器，32状态维特比检测器最佳奇偶校验处理器，鲁棒帧同步，自适应均衡，热粗糙度检测和补偿，自适应磁阻不对称补偿，低延迟内插时序恢复和可编程预写。

3. 发明授权

US06549354B1 Acquisition signal error estimator 有权
公开(公告)号：US06549354B1
公开(公告)日：2003-04-15
申请号：US09653235
申请日：2000-08-31
申请人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
发明人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
IPC分类号： G11B509
CPC分类号： G11B20/10037 , G11B5/09 , G11B20/10009 , G11B20/10055 , G11B20/22
摘要： A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample value. According to one embodiment, four consecutive samples are used. According to another embodiment, two samples are used. The acquisition signal error estimator maybe used in conjunction with gain, DC offset, or magneto-resistive asymmetry control loops in a sampled amplitude read channel.

4. 发明授权

US07137056B2 Low error propagation rate 32/34 trellis code 有权
标题翻译：低误差传播率32/34格状码
公开(公告)号：US07137056B2
公开(公告)日：2006-11-14
申请号：US10253903
申请日：2002-09-25
申请人： Jonathan Ashley , William G. Bliss , Razmik Karabed , Kaichi Zhang
发明人： Jonathan Ashley , William G. Bliss , Razmik Karabed , Kaichi Zhang
IPC分类号： H03M13/00
CPC分类号： H04L1/006 , H03M5/145 , H03M13/41 , H04L1/0041 , H04L1/0054
摘要： The present invention relates to a coding system characterized by various combinations of the following properties: 1) Even parity at the output of d of the precoder; 2) A coding rate of 32/34; 3) At least 9 ones per codeword; 4) No more than 13 consecutive zeros in the stream of encoded data (G=13); 5) No more than 13 consecutive zeros in any run of every-other-bit in the stream of codewords (I=13); 6) For closed error events in y or y′ having squared-distance≦(1 to 1.5)×dmfb2 in the detector, the decoder produces at most 4 corresponding erroneous data bytes; 7) Decoding of a 34 bit codeword may begin when 19 of its bits have been received; 8) If the Viterbi detector 108 outputs Non-Return to Zero (NRZ) symbols, then its output is filtered by (1⊕D^2) before being decoded, but if the Viterbi detector outputs NRZ Inverter (NRZI) symbols, then its output is decoded directly; and 9) The even parity is on NRZ symbols.
摘要翻译：本发明涉及以下特性的各种组合为特征的编码系统：1）预编码器d的输出端的偶校验; 2）编码率32/34; 3）每个码字至少有9个; 4）编码数据流中不超过13个连续的零（G = 13）; 5）代码字流（I = 13）中每个其他位的任何运行中不超过13个连续的零; 6）对于检测器中y或y'具有平方距离<=（1到1.5）xD mfb 2> / 2>的闭合误差事件，解码器产生最多4个相应的错误的数据字节; 7）当接收到其位的19个时，可以开始对34位码字的解码; 8）如果维特比检测器108输出非归零（NRZ）符号，则在解码之前将其输出滤波为（1⊕D^ 2），但是如果维特比检测器输出NRZ变换器（NRZI）符号，则其输出直接解码; 和9）偶数奇偶校验位在NRZ符号上。

5. 发明授权

US06774825B2 Modulation coding based on an ECC interleave structure 失效
标题翻译：基于ECC交错结构的调制编码
公开(公告)号：US06774825B2
公开(公告)日：2004-08-10
申请号：US10253909
申请日：2002-09-25
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed , Ali Najafi , Jonathan Ashley
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed , Ali Najafi , Jonathan Ashley
IPC分类号： H03M700
CPC分类号： H03M13/27 , G11B20/1426 , G11B20/1833 , G11B20/1866 , H03M5/145
摘要： A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.
摘要翻译：基于ECC交错结构来调制编码的系统和方法包括编码包括被排序成交织的输入块的位的输入流的第一编码器。第二编码器编码输入块的子集以产生输出块，其中第一编码器排列剩余的输入块和输出块以产生码字。

6. 发明授权

US06680980B1 Supporting ME2PRML and M2EPRML with the same trellis structure 有权
标题翻译：支持具有相同网格结构的ME2PRML和M2EPRML
公开(公告)号：US06680980B1
公开(公告)日：2004-01-20
申请号：US09503534
申请日：2000-02-14
申请人： Jonathan Ashley , Razmik Karabed
发明人： Jonathan Ashley , Razmik Karabed
IPC分类号： H04L512
CPC分类号： H03M13/6343 , H03M13/4107 , H03M13/6502 , H04L25/03178 , H04L25/497
摘要： A Viterbi trellis is provided which allows for implementation of either an EPRML type channel or an E2PRML type channel using a single trellis structure. According to a specific embodiment, a trellis is provided which can support a 0 mod 2 EPRML (M2EPRML) channel and a modified E2PRML (ME2PRML) channel.
摘要翻译：提供维特比网格，其允许使用单个网格结构来实现EPRML类型信道或E2PRML类型信道。根据具体实施例，提供了可以支持0模2 EPRML（M2EPRML）信道和修改的E2PRML（ME2PRML）信道的网格。

7. 发明授权

US06469851B1 Acquisition signal error estimator 有权
标题翻译：采集信号误差估计器
公开(公告)号：US06469851B1
公开(公告)日：2002-10-22
申请号：US09480314
申请日：2000-01-10
申请人： Jonathan Ashley , Stephen J. Franck
发明人： Jonathan Ashley , Stephen J. Franck
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/22
摘要： A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample value. According to one embodiment, four consecutive samples are used. According to another embodiment, two samples are used. The acquisition signal error estimator maybe used in conjunction with gain, DC offset, or magneto-resistive asymmetry control loops in a sampled amplitude read channel.
摘要翻译：提供了一种用于采集信号误差估计的系统和方法，其使用该序列的一个或多个过去值来确定最接近的理想样本值。根据一个实施例，使用四个连续的样本。根据另一个实施例，使用两个样本。采集信号误差估计器可以与采样幅度读通道中的增益，直流偏移或磁阻不对称控制环路结合使用。

8. 发明授权

US06587292B1 Magneto-resistive asymmetry compensation loop 有权
标题翻译：磁阻不对称补偿回路
公开(公告)号：US06587292B1
公开(公告)日：2003-07-01
申请号：US09546796
申请日：2000-04-11
申请人： Jonathan Ashley , James Wilson Rae , Stephen J. Franck
发明人： Jonathan Ashley , James Wilson Rae , Stephen J. Franck
IPC分类号： G11B5035
CPC分类号： G11B20/10055 , G11B5/09 , G11B20/10009 , G11B20/22
摘要： A magneto-resistive asymmetry compensation system includes a linearizer (61) interposed in a data path and a control loop (63). The control loop uses signal estimates from an interpolated timing response unit (25) to derive a magneto-resistive asymmetry error. The error term is used to obtain a control scaling input to the linearizer. The linearizer functions to multiply the scaling multiple to the square of the input signal and then add it back to the input signal.
摘要翻译：磁阻非对称补偿系统包括插入在数据路径中的线性化器（61）和控制回路（63）。控制环路使用来自内插定时响应单元（25）的信号估计来导出磁阻非对称误差。误差项用于获得对线性化器的控制缩放输入。线性化器用于将缩放倍数乘以输入信号的平方，然后将其添加回输入信号。

9. 发明申请

US20090285662A1 SIDE RECOVERY SYSTEM FOR A VEHICLE 有权
标题翻译：车辆侧面恢复系统
公开(公告)号：US20090285662A1
公开(公告)日：2009-11-19
申请号：US12271774
申请日：2008-11-14
申请人： Jeffrey L. Addleman , Jonathan Ashley , Sanjeev Kuriakose , Jeffrey L. Weller
发明人： Jeffrey L. Addleman , Jonathan Ashley , Sanjeev Kuriakose , Jeffrey L. Weller
IPC分类号： B60P3/12
CPC分类号： B60P3/12 , B66C23/80
摘要： A side recovery system is disclosed that includes a base configured to be supported on a vehicle and a boom supported by the base and having a first end and a second end. The boom is rotatable relative to the base about a substantially horizontal axis between a first position and second position. The second end of the boom being positioned at a first side of the vehicle in the first position and at an opposite second side of the vehicle in the second position. The system also includes a first sheave supported at the second end of the boom and configured to receive a load bearing cable. The cable configured to remain received by the first sheave as the boom rotates between the first position and the second position.
摘要翻译：公开了一种侧面回收系统，其包括构造成被支撑在车辆上的基座和由基座支撑并具有第一端和第二端的起重臂。吊臂可相对于基座围绕第一位置和第二位置之间的基本上水平的轴线旋转。动臂的第二端在第一位置处位于车辆的第一侧，并且在第二位置处位于车辆的相对的第二侧。该系统还包括支撑在起重臂的第二端处并构造成接收承重电缆的第一滑轮。所述电缆构造为当所述吊臂在所述第一位置和所述第二位置之间旋转时由所述第一滑轮保持接收。

10. 发明申请

US20060212783A1 Method and apparatus for combined encoder/syndrome computer with programmable parity level 有权
公开(公告)号：US20060212783A1
公开(公告)日：2006-09-21
申请号：US11079634
申请日：2005-03-14
申请人： Jonathan Ashley , Clifton Williamson
发明人： Jonathan Ashley , Clifton Williamson
IPC分类号： H03M13/00
CPC分类号： H03M13/159
摘要： Methods and apparatus are provided for a combined encoder/syndrome computer with a programmable parity level. In one embodiment, a circuit is disclosed that generates check symbols during an encoding operation and generates error syndromes during a decoding operation. The circuit comprises a plurality of subfilters grouped into a multiple degree polynomial filter, where the number of multiple degree subfilters is less than a maximum number of symbols of redundancy.

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