专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06544801B1 Method of fabricating thermally stable MTJ cell and apparatus 有权
标题翻译：制造热稳定MTJ电池及其装置的方法
公开(公告)号：US06544801B1
公开(公告)日：2003-04-08
申请号：US09642350
申请日：2000-08-21
申请人： Jon Slaughter , Saied Tehrani , Eugene Chen , Mark Durlam , Mark DeHerrera , Renu Whig Dave
发明人： Jon Slaughter , Saied Tehrani , Eugene Chen , Mark Durlam , Mark DeHerrera , Renu Whig Dave
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y10/00
摘要： An MTJ cell including an insulator layer of material between magnetic material layers with the insulator layer of material having a greater attraction for a third material than the magnetic material layers. The third material is introduced to one or both so that when the cell is heated the third material is redistributed from the magnetic material layer to the insulator layer. Upon redistribution the insulator layer becomes an insulator layer material. Also, a first diffusion barrier layer is positioned between a first metal electrode and one of the magnetic material layers and/or a second diffusion barrier layer is positioned between a second metal electrode and the other magnetic material layer to prevent diffusion of the metal in the electrodes into the magnetic material layers.
摘要翻译： MTJ单元包括在磁性材料层之间的材料的绝缘体层，材料的绝缘体层对于第三材料具有比磁性材料层更大的吸引力。将第三材料引入一个或两个，使得当电池被加热时，第三材料从磁性材料层重新分布到绝缘体层。在再分配时，绝缘体层变成绝缘体层材料。此外，第一扩散阻挡层位于第一金属电极和一个磁性材料层之间，和/或第二扩散阻挡层位于第二金属电极和另一个磁性材料层之间，以防止金属在电极进入磁性材料层。

2. 发明授权

US06365419B1 High density MRAM cell array 失效
标题翻译：高密度MRAM单元阵列
公开(公告)号：US06365419B1
公开(公告)日：2002-04-02
申请号：US09649114
申请日：2000-08-28
申请人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
发明人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00 , H01L43/12
摘要： A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.
摘要翻译：制造MRAM单元的方法包括在半导体衬底上提供隔离晶体管，并在衬底上形成与晶体管的一个端子连通的互连叠层。通孔形成在堆叠的上端，以从数字线下方的位置延伸到数字线上方的位置。通孔也延伸到电介质层的上表面之上，以提供对准键。 MTJ存储单元位于与通孔接触的上表面上，并且通过使用侧壁间隔件和选择性蚀刻，磁性材料的自由层的端部与磁性材料的被钉扎边缘的端部间隔开。

3. 发明授权

US06331943B1 MTJ MRAM series-parallel architecture 失效
标题翻译： MTJ MRAM系列并行架构
公开(公告)号：US06331943B1
公开(公告)日：2001-12-18
申请号：US09649117
申请日：2000-08-28
申请人： Peter K. Naji , Mark DeHerrera , Mark Durlam
发明人： Peter K. Naji , Mark DeHerrera , Mark Durlam
IPC分类号： G11C1100
CPC分类号： H01L27/228 , G11C11/15
摘要： Magnetic tunnel junction random access memory architecture in which an array of memory cells is arranged in rows and columns and each memory cell includes a magnetic tunnel junction and a control transistor connected in parallel. A control line is connected to the gate of each control transistor in a row of control transistors and a metal programming line extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines. The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.
摘要翻译：磁性隧道结随机存取存储器结构，其中存储器单元阵列以行和列排列，并且每个存储单元包括并行连接的磁性隧道结和控制晶体管。控制线连接到一排控制晶体管中的每个控制晶体管的栅极，并且与每个磁性隧道结相邻的金属编程线通过通孔以间隔开的间隔连接到控制线。此外，每列中的存储单元组被串联连接以形成与全局位线并行连接的局部位线。使用位于中心的列来读取串并联配置以提供参考信号，并且将参考列的每一侧的列中的数据与参考信号进行比较或差异地比较两个接近的列。

4. 发明授权

US06233172B1 Magnetic element with dual magnetic states and fabrication method thereof 有权
标题翻译：具有双磁状态的磁性元件及其制造方法
公开(公告)号：US06233172B1
公开(公告)日：2001-05-15
申请号：US09464807
申请日：1999-12-17
申请人： Eugene Youjun Chen , Jon Michael Slaughter , Mark Durlam , Mark DeHerrera , Saied N. Tehrani
发明人： Eugene Youjun Chen , Jon Michael Slaughter , Mark Durlam , Mark DeHerrera , Saied N. Tehrani
IPC分类号： G11C1115
CPC分类号： H01F10/3254 , B82Y25/00 , G11C11/16 , H01F10/3272
摘要： An improved and novel magnetic element (10; 10′; 50; 50′; 80) including a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field. Additionally disclosed is a method of fabricating a magnetic element (10) by providing a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields of the thin film layers cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field.
摘要翻译：包括多个薄膜层的改进和新颖的磁性元件（10; 10'; 50; 50'; 80），其中所述位端磁静电消磁场抵消所述结构的总正耦合以获得双重磁状态零外场。另外公开了一种通过提供多个薄膜层来制造磁性元件（10）的方法，其中薄膜层的位端磁静电消磁场抵消该结构的总正耦合以获得双重磁状态零外场。

5. 发明授权

US06912107B2 Magnetic element with insulating veils and fabricating method thereof 失效
标题翻译：具有绝缘面纱的磁性元件及其制造方法
公开(公告)号：US06912107B2
公开(公告)日：2005-06-28
申请号：US10830264
申请日：2004-04-21
申请人： Eugene Youjun Chen , Mark Durlam , Saied N. Tehrani , Mark DeHerrera , Gloria Kerszykowski , Kelly Wayne Kyler
发明人： Eugene Youjun Chen , Mark Durlam , Saied N. Tehrani , Mark DeHerrera , Gloria Kerszykowski , Kelly Wayne Kyler
IPC分类号： G11B5/39 , H01F10/32 , H01F41/30 , H01L21/8246 , H01L27/105 , H01L43/08 , G11B5/127
CPC分类号： B82Y25/00 , B82Y40/00 , H01F10/324 , H01F41/302 , H01L43/12 , Y10T29/49044 , Y10T29/49046 , Y10T29/49052 , Y10T428/24917
摘要： An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element (10) with insulative veils (34) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.
摘要翻译：一种用于磁性元件的改进和新颖的器件和制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。第一电极（14）和第二电极（18）包括铁磁层（26和28）。间隔层（16）位于第一电极（14）的铁磁层（26）和第二电极（16）的铁磁层（28）之间，用于允许隧道电流沿大致垂直于铁磁层的方向 26和28）。该装置包括绝缘面纱（34），其特征在于电隔离第一电极（14）和第二电极（18），绝缘面纱（34）包括非磁性和绝缘的介电性质。另外公开了一种通过氧等离子体灰化技术制造具有绝缘面纱（34）的磁性元件（10）的方法，其已经从具有导电性能转变为绝缘性能。

6. 发明授权

US06835423B2 Method of fabricating a magnetic element with insulating veils 有权
标题翻译：制造具有绝缘面纱的磁性元件的方法
公开(公告)号：US06835423B2
公开(公告)日：2004-12-28
申请号：US10349702
申请日：2003-01-22
申请人： Eugene Youjun Chen , Mark Durlam , Saied N. Tehrani , Mark DeHerrera , Gloria Kerszykowski , Kelly Wayne Kyler
发明人： Eugene Youjun Chen , Mark Durlam , Saied N. Tehrani , Mark DeHerrera , Gloria Kerszykowski , Kelly Wayne Kyler
IPC分类号： H05H100
CPC分类号： B82Y25/00 , B82Y40/00 , H01F10/324 , H01F41/302 , H01L43/12 , Y10T29/49044 , Y10T29/49046 , Y10T29/49052 , Y10T428/24917
摘要： An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element (10) with insulative veils (34) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.
摘要翻译：一种用于磁性元件的改进和新颖的器件和制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。第一电极（14）和第二电极（18）包括铁磁层（26和28）。间隔层（16）位于第一电极（14）的铁磁层（26）和第二电极（16）的铁磁层（28）之间，用于允许隧道电流沿大致垂直于铁磁层的方向 26和28）。该装置包括绝缘面纱（34），其特征在于电隔离第一电极（14）和第二电极（18），绝缘面纱（34）包括非磁性和绝缘的介电性质。另外公开了一种通过氧等离子体灰化技术制造具有绝缘面纱（34）的磁性元件（10）的方法，其已经从具有导电性能转变为绝缘性能。

7. 发明申请

US20050133822A1 Apparatus for pulse testing a MRAM device and method therefore 失效
标题翻译：用于脉冲测试MRAM器件的方法及方法
公开(公告)号：US20050133822A1
公开(公告)日：2005-06-23
申请号：US10746014
申请日：2003-12-23
申请人： Mark DeHerrera , Nicholas Rizzo
发明人： Mark DeHerrera , Nicholas Rizzo
IPC分类号： G11C29/50 , G11C29/56 , H01L31/072
CPC分类号： G11C29/56 , G11C11/16 , G11C29/50
摘要： Methods and apparatus are provided for testing a magnetoresistive random access memory (MRAM). A magnetoresistive tunnel junction (MTJ) has a first terminal, a second terminal, and a third terminal. A source measuring unit is coupled to a first terminal of a MTJ to provide DC biasing. A current preamp has an input coupled to a third terminal of the MTJ for receiving current corresponding to a resistance of the MTJ. A pulse generator is AC coupled to the MTJ for programming the MTJ. A method of insitu testing a MTJ in a manufacturing environment uses a probe station coupled to the MTJ. A probe station couples to the MTJ. The MTJ is DC biased for generating a current corresponding to the logic level stored in the MTJ. A pulse for programming the MTJ is AC coupled to the MTJ.
摘要翻译：提供了用于测试磁阻随机存取存储器（MRAM）的方法和装置。磁阻隧道结（MTJ）具有第一端子，第二端子和第三端子。源测量单元耦合到MTJ的第一端以提供DC偏置。电流前置放大器具有耦合到MTJ的第三端子的输入，用于接收对应于MTJ的电阻的电流。脉冲发生器与MTJ交流耦合，用于对MTJ进行编程。在制造环境中对MTJ进行实地测试的方法使用耦合到MTJ的探测台。探测台耦合到MTJ。 MTJ被直流偏置以产生对应于存储在MTJ中的逻辑电平的电流。用于编程MTJ的脉冲与MTJ交流耦合。

8. 发明授权

US07333360B2 Apparatus for pulse testing a MRAM device and method therefore 失效
标题翻译：用于脉冲测试MRAM器件的方法及方法
公开(公告)号：US07333360B2
公开(公告)日：2008-02-19
申请号：US10746014
申请日：2003-12-23
申请人： Mark DeHerrera , Nicholas Rizzo
发明人： Mark DeHerrera , Nicholas Rizzo
IPC分类号： G11C11/15
CPC分类号： G11C29/56 , G11C11/16 , G11C29/50
摘要： Methods and apparatus are provided for testing a magnetoresistive random access memory (MRAM). A magnetoresistive tunnel junction (MTJ) has a first terminal, a second terminal, and a third terminal. A source measuring unit is coupled to a first terminal of a MTJ to provide DC biasing. A current preamp has an input coupled to a third terminal of the MTJ for receiving current corresponding to a resistance of the MTJ. A pulse generator is AC coupled to the MTJ for programming the MTJ. A method of insitu testing a MTJ in a manufacturing environment uses a probe station coupled to the MTJ. A probe station couples to the MTJ. The MTJ is DC biased for generating a current corresponding to the logic level stored in the MTJ. A pulse for programming the MTJ is AC coupled to the MTJ.
摘要翻译：提供了用于测试磁阻随机存取存储器（MRAM）的方法和装置。磁阻隧道结（MTJ）具有第一端子，第二端子和第三端子。源测量单元耦合到MTJ的第一端以提供DC偏置。电流前置放大器具有耦合到MTJ的第三端子的输入，用于接收对应于MTJ的电阻的电流。脉冲发生器与MTJ交流耦合，用于对MTJ进行编程。在制造环境中对MTJ进行实地测试的方法使用耦合到MTJ的探测台。探测台耦合到MTJ。 MTJ被直流偏置以产生对应于存储在MTJ中的逻辑电平的电流。用于编程MTJ的脉冲与MTJ交流耦合。

9. 发明申请

US20050128795A1 Reducing power consumption during MRAM writes using multiple current levels 失效
标题翻译：使用多个电流电平降低MRAM写入期间的功耗
公开(公告)号：US20050128795A1
公开(公告)日：2005-06-16
申请号：US10737114
申请日：2003-12-16
申请人： Mark DeHerrera , Bengt Akerman
发明人： Mark DeHerrera , Bengt Akerman
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/16
摘要： A reduced power method of writing MRAM bits is disclosed. The reduced power method includes writing MRAM bits by applying a first magnetic field having a low magnitude, then determining if the bit has switched. If not, a second magnetic field having a higher magnitude is applied. Applying magnetic fields to an MRAM bit cell is accomplished by sending a current pulse through a strip line adjacent to the MRAM bit cell. The technique can be performed for every write to an MRAM bit. Alternatively, the weaker magnetic field can be applied during system test or system initialization, and if the weaker field fails to write the bit to a desired value, the failing result is stored and each subsequent write to the MRAM bit utilizes the stronger magnetic field.
摘要翻译：公开了一种写入MRAM位的降低功耗的方法。降低功率方法包括通过施加具有低幅度的第一磁场来写入MRAM位，然后确定该位是否已切换。如果不是，则施加具有较大幅度的第二磁场。将磁场施加到MRAM位单元是通过将电流脉冲发送到与MRAM位单元相邻的带状线来实现的。可以对每次写入MRAM位执行该技术。或者，较弱的磁场可以在系统测试或系统初始化期间应用，如果较弱的磁场无法将该位写入所需的值，则存储故障结果，并且每次对MRAM位的后续写入都会使用更强的磁场。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式