专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6118163A Transistor with integrated poly/metal gate electrode 失效
标题翻译：具有集成多晶/金属栅电极的晶体管
公开(公告)号：US6118163A
公开(公告)日：2000-09-12
申请号：US17720
申请日：1998-02-04
申请人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
发明人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28061 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.
摘要翻译：提供集成电路晶体管及其制造方法。晶体管包括衬底，第一和第二源极/漏极区域以及耦合到衬底的栅电极堆叠。通过在基板上形成第一绝缘层，在第一绝缘层上形成第一导体层，在第一导体层上形成金属层，制作栅电极堆叠。诸如层间电介质层的第二绝缘层耦合到与栅电极堆叠相邻的衬底。可以并入侧壁间隔物和LDD处理。晶体管和方法将金属和多晶硅集成到自对准栅极电极堆叠中。

2. 发明授权

US5981365A Stacked poly-oxide-poly gate for improved silicide formation 失效
标题翻译：用于改善硅化物形成的堆叠多晶氧化物多晶硅栅极
公开(公告)号：US5981365A
公开(公告)日：1999-11-09
申请号：US37530
申请日：1998-03-10
申请人： Jon D. Cheek , Derick J. Wristers , Mark I. Gardner
发明人： Jon D. Cheek , Derick J. Wristers , Mark I. Gardner
IPC分类号： H01L21/336 , H01L21/285
CPC分类号： H01L29/6659 , H01L29/41783 , H01L29/665 , H01L29/66545
摘要： A method of fabricating an integrated circuit transistor in a substrate is provided. A gate electrode stack is formed on the substrate. The stack has a first insulating layer, a first conductor layer on the first insulating layer, a second insulating layer on the first conductor layer, and a second conductor layer on the second insulating layer. First and second source/drain regions are formed in the substrate in spaced apart relation to define a channel region underlying the first insulating layer. First and second sidewall spacers are formed adjacent to the gate electrode stack. The second conductor layer and the second insulating layer are sacrificed and a silicide layer is formed on the first conductor layer. The void remaining after removal of the second conductor and insulating layers establishes a large separation between the silicide forming titanium layer and the first conductor layer. The result is a gate electrode stack that is resistant to lateral silicide formation due to silicon diffusion.
摘要翻译：提供了一种在衬底中制造集成电路晶体管的方法。在基板上形成栅电极堆叠。叠层具有第一绝缘层，第一绝缘层上的第一导体层，第一导体层上的第二绝缘层和第二绝缘层上的第二导体层。第一和第二源极/漏极区域以间隔开的关系形成在衬底中，以限定第一绝缘层下面的沟道区域。第一和第二侧壁间隔件邻近栅电极堆叠形成。牺牲第二导体层和第二绝缘层，在第一导体层上形成硅化物层。在去除第二导体和绝缘层之后残留的空隙在硅化物形成钛层和第一导体层之间形成大的间隔。结果是由于硅扩散而耐外部硅化物形成的栅电极堆叠。

3. 发明授权

US5994193A Method of making high performance MOSFET with integrated poly/metal gate electrode 失效
标题翻译：制造具有集成多晶/金属栅电极的高性能MOSFET的方法
公开(公告)号：US5994193A
公开(公告)日：1999-11-30
申请号：US95088
申请日：1998-06-10
申请人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
发明人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/28061 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.
摘要翻译：提供集成电路晶体管及其制造方法。晶体管包括衬底，第一和第二源极/漏极区域以及耦合到衬底的栅电极堆叠。通过在基板上形成第一绝缘层，在第一绝缘层上形成第一导体层，在第一导体层上形成金属层，制作栅电极堆叠。诸如层间电介质层的第二绝缘层耦合到与栅电极堆叠相邻的衬底。可以并入侧壁间隔物和LDD处理。晶体管和方法将金属和多晶硅集成到自对准栅极电极堆叠中。

4. 发明授权

US06566696B1 Self-aligned VT implant 有权
标题翻译：自对准VT植入
公开(公告)号：US06566696B1
公开(公告)日：2003-05-20
申请号：US09907359
申请日：2001-07-17
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L2980
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供了具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

5. 发明授权

US06018180A Transistor formation with LI overetch immunity 失效
标题翻译：晶体管形成与LI过滤免疫
公开(公告)号：US06018180A
公开(公告)日：2000-01-25
申请号：US996648
申请日：1997-12-23
申请人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/762 , H01L21/768 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/76224
摘要： An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.
摘要翻译：提供一种集成电路晶体管及其制造方法。晶体管由于局部互连沟槽的过蚀刻而抵抗结短路。该晶体管包括具有第一结的源极/漏极区域和位于有源区域的易于经过过渡接合短路现象的部分中比第一结点更深的第二结点。第二结通过通过掩模的离子注入建立，其被图案化以产生对应于有源区和局部互连沟槽的布局的交点的开口。使用该方法，仅在需要防止短路并且不妨碍晶体管性能的情况下才建立第二结。

6. 发明授权

US06580122B1 Transistor device having an enhanced width dimension and a method of making same 有权
标题翻译：具有增强的宽度尺寸的晶体管器件及其制造方法
公开(公告)号：US06580122B1
公开(公告)日：2003-06-17
申请号：US09812521
申请日：2001-03-20
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L2976
CPC分类号： G01N27/414
摘要： The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.
摘要翻译：本发明涉及一种具有增强的宽度尺寸的晶体管及其制造方法。在一个说明性实施例中，晶体管包括半导体衬底，形成在衬底中的凹陷隔离结构，隔离结构在其上限定凹陷，栅电极和位于衬底上方的栅极绝缘层，栅电极的一部分和栅极绝缘层延伸到凹陷隔离结构上方的凹部中，以及形成在衬底中的源极区域和漏极区域。在另一示例性实施例中，晶体管包括半导体衬底，限定具有上表面和暴露侧壁表面的有源区的凹陷隔离结构，位于上表面的一部分上方的栅绝缘层和栅电极，的有源区域的暴露的侧壁表面，以及形成在有源区域中的源极区域和漏极区域。

7. 发明授权

US06372587B1 Angled halo implant tailoring using implant mask 有权
标题翻译：使用植入物掩模的角度光晕植入物定制
公开(公告)号：US06372587B1
公开(公告)日：2002-04-16
申请号：US09568069
申请日：2000-05-10
申请人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
发明人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness &tgr; above the surface and having an edge disposed a distance &dgr; from the first edge of the structure. The method also includes implanting the halo implant at an angle &agr; with respect to a direction perpendicular to the surface, wherein the tangent of the angle &agr; is at least the ratio of the distance &dgr; to the thickness &tgr;.
摘要翻译：提供了一种用于在邻近结构的一侧的衬底中形成卤素注入的方法，所述方法包括在所述衬底的表面上方形成所述结构，所述结构具有第一和第二边缘并且形成限定邻近所述结构的区域的掩模，该面具具有厚度＆tgr; 并且具有与结构的第一边缘相距一定距离的边缘。该方法还包括将晕圈植入物相对于垂直于该表面的方向以角度α注入，其中角度α的切线至少为距离δ与厚度的比值。

8. 发明授权

US06346426B1 Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements 失效
标题翻译：基于独立临界尺寸测量来表征半导体器件性能变化的方法和装置
公开(公告)号：US06346426B1
公开(公告)日：2002-02-12
申请号：US09716181
申请日：2000-11-17
申请人： Anthony J. Toprac , Derick J. Wristers , Jon D. Cheek
发明人： Anthony J. Toprac , Derick J. Wristers , Jon D. Cheek
IPC分类号： H01L2100
CPC分类号： H01L22/26 , H01L22/12
摘要： A method for characterizing semiconductor device performance variations includes processing a wafer in a processing line to form a feature on the wafer; measuring a physical critical dimension of the feature in a first metrology tool to generate a first critical dimension measurement; measuring the physical critical dimension of the feature in a second metrology tool to generate a second critical dimension measurement independent of the first critical dimension measurement; determining an effective critical dimension of the feature in a third metrology tool to generate a third critical dimension measurement; and comparing the first, second, and third critical dimension measurements to identify a metrology drift in one of the first and second metrology tools. A system for characterizing semiconductor device performance variations includes a processing line, first, second, and third metrology tools, and a process controller. The processing line is adapted to process a wafer to form a feature on the wafer. The first metrology tool is adapted to measure a physical critical dimension of the feature to generate a first critical dimension measurement. The second metrology tool is adapted to measure the physical critical dimension of the feature to generate a second critical dimension measurement independent of the first critical dimension measurement. The third metrology tool adapted to determine an effective critical dimension of the feature to generate a third critical dimension measurement. The process controller is adapted to compare the first, second, and third critical dimension measurements to identify a metrology drift in one of the first and second metrology tools.
摘要翻译：用于表征半导体器件性能变化的方法包括处理处理线中的晶片以在晶片上形成特征; 测量第一计量工具中的特征的物理临界尺寸以产生第一临界尺寸测量; 在第二计量工具中测量所述特征的物理临界尺寸以产生独立于所述第一临界尺寸测量的第二临界尺寸测量; 确定第三计量工具中的特征的有效临界尺寸以产生第三临界尺寸测量; 以及比较所述第一，第二和第三临界尺寸测量值以识别所述第一和第二测量工具之一中的度量漂移。用于表征半导体器件性能变化的系统包括处理线，第一，第二和第三计量工具以及过程控制器。处理线适于处理晶片以在晶片上形成特征。第一计量工具适用于测量特征的物理关键尺寸以产生第一临界尺寸测量。第二计量工具适于测量特征的物理临界尺寸以产生独立于第一临界尺寸测量的第二临界尺寸测量。第三计量工具适于确定特征的有效临界尺寸以产生第三临界尺寸测量。过程控制器适于比较第一，第二和第三关键尺寸测量值以识别第一和第二计量工具之一中的度量漂移。

9. 发明授权

US06274415B1 Self-aligned Vt implant 有权
标题翻译：自对准Vt植入物
公开(公告)号：US06274415B1
公开(公告)日：2001-08-14
申请号：US09489068
申请日：2000-01-21
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L21337
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

10. 发明授权

US06261936B1 Poly gate CD passivation for metrology control 有权
标题翻译：聚门CD钝化用于计量控制
公开(公告)号：US06261936B1
公开(公告)日：2001-07-17
申请号：US09589378
申请日：2000-06-07
申请人： Marilyn I. Wright , Derick J. Wristers , Jon D. Cheek
发明人： Marilyn I. Wright , Derick J. Wristers , Jon D. Cheek
IPC分类号： H01L214763
CPC分类号： H01L21/28123 , H01L21/32105
摘要： Various methods of fabricating gate structures, such as gates and gate stacks are provided. In one aspect, a method of fabricating a gate electrode on a substrate is provided that includes depositing a polycrystalline silicon film on the substrate and etching the polycrystalline film into a desired shape with a first sidewall and a second and opposite sidewall. A passivating oxide film is formed with a preselected thickness on the first and second sidewalls by oxidizing the silicon structure with a heated aqueous solution of ammonium hydroxide and hydrogen peroxide. Gate electrode formation with an oxide coating film of known thickness is provided. Linewidth metrology accuracy may be improved.
摘要翻译：提供制造栅极结构的各种方法，例如栅极和栅极叠层。在一个方面，提供了一种在衬底上制造栅电极的方法，其包括在衬底上沉积多晶硅膜并用第一侧壁和第二相对侧壁将多晶膜蚀刻成所需形状。通过用氢氧化铵和过氧化氢的加热水溶液氧化硅结构，在第一和第二侧壁上形成预定厚度的钝化氧化物膜。提供具有已知厚度的氧化物涂膜的栅电极形成。可以提高线宽度量精度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式