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1. 发明授权

US06890815B2 Reduced cap layer erosion for borderless contacts 失效
标题翻译：减少无边界接触的盖层侵蚀
公开(公告)号：US06890815B2
公开(公告)日：2005-05-10
申请号：US10655199
申请日：2003-09-04
申请人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir D. Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
发明人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir D. Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
IPC分类号： H01L21/60 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.
摘要翻译：形成无边界接触的方法和用于半导体器件的无边界接触结构。优选实施例包括使用设置在第一蚀刻选择性材料上的第二蚀刻选择性材料，以在半导体器件的各种材料层的蚀刻工艺期间保持第一蚀刻选择性材料，同时形成无边界接触。

2. 发明申请

US20050051839A1 REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS 失效
标题翻译：减少无边界接触层的层次腐蚀
公开(公告)号：US20050051839A1
公开(公告)日：2005-03-10
申请号：US10655199
申请日：2003-09-04
申请人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
发明人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
IPC分类号： H01L21/60 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.
摘要翻译：形成无边界接触的方法和用于半导体器件的无边界接触结构。优选实施例包括使用设置在第一蚀刻选择性材料上的第二蚀刻选择性材料，以在半导体器件的各种材料层的蚀刻工艺期间保持第一蚀刻选择性材料，同时形成无边界接触。

3. 发明申请

US20050077562A1 SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS 失效
标题翻译：自定义阵列与记忆体的联系
公开(公告)号：US20050077562A1
公开(公告)日：2005-04-14
申请号：US10605590
申请日：2003-10-10
申请人： Rama Divakaruni , Johnathan Faltermeier , Michael Maldei , Jay Strane
发明人： Rama Divakaruni , Johnathan Faltermeier , Michael Maldei , Jay Strane
IPC分类号： H01L21/60 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897
摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.
摘要翻译：提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。在槽中形成与基板和位线的位线接触。此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

4. 发明授权

US06746933B1 Pitcher-shaped active area for field effect transistor and method of forming same 失效
公开(公告)号：US06746933B1
公开(公告)日：2004-06-08
申请号：US09999803
申请日：2001-10-26
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

5. 发明授权

US06960514B2 Pitcher-shaped active area for field effect transistor and method of forming same 失效
标题翻译：投币型场效应晶体管及其形成方法
公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译：对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部区域结构。本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

6. 发明授权

US06509624B1 Semiconductor fuses and antifuses in vertical DRAMS 有权
标题翻译：垂直DRAMS中的半导体熔断器和反熔丝
公开(公告)号：US06509624B1
公开(公告)日：2003-01-21
申请号：US09675246
申请日：2000-09-29
申请人： Carl J. Radens , Wolfgang Bergner , Rama Divakaruni , Larry Nesbit
发明人： Carl J. Radens , Wolfgang Bergner , Rama Divakaruni , Larry Nesbit
IPC分类号： H01L2900
CPC分类号： H01L27/10861 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology.
摘要翻译：垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括接触半导体插头的导电引线。反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。每个熔丝和反熔丝都是使用一系列工艺操作来制造的，这些工序也用于根据垂直DRAM技术同时制造垂直晶体管。

7. 发明授权

US06184107B2 Capacitor trench-top dielectric for self-aligned device isolation 有权
标题翻译：用于自对准器件隔离的电容器沟槽电介质
公开(公告)号：US06184107B2
公开(公告)日：2001-02-06
申请号：US09271124
申请日：1999-03-17
申请人： Rama Divakaruni , Ulrike Gruening , Byeong Y. Kim , Jack A. Mandelman , Larry Nesbit , Carl J. Radens
发明人： Rama Divakaruni , Ulrike Gruening , Byeong Y. Kim , Jack A. Mandelman , Larry Nesbit , Carl J. Radens
IPC分类号： H01L2176
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.
摘要翻译：一种包括衬底的半导体器件。至少一对深沟槽布置在衬底中。每个深沟槽的壁的至少一部分的领子。深沟槽填充每个深沟槽。埋藏的带子完全延伸穿过每个深沟槽填充物和每个环圈的每个深沟槽。隔离区域布置在深沟槽之间。电介质区域覆盖每个深沟槽中的每个掩埋带。

8. 发明授权

US06620676B2 Structure and methods for process integration in vertical DRAM cell fabrication 有权
标题翻译：垂直DRAM单元制造过程集成的结构和方法
公开(公告)号：US06620676B2
公开(公告)日：2003-09-16
申请号：US09895672
申请日：2001-06-29
申请人： Rajeev Malik , Larry Nesbit , Jochen Beintner , Rama Divakaruni
发明人： Rajeev Malik , Larry Nesbit , Jochen Beintner , Rama Divakaruni
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/76224 , H01L27/10861
摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
摘要翻译：公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。然而，支撑区域中的初始衬垫氮化物材料仍然保持。然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

9. 发明授权

US06870211B1 Self-aligned array contact for memory cells 失效
标题翻译：用于存储单元的自对准阵列触点
公开(公告)号：US06870211B1
公开(公告)日：2005-03-22
申请号：US10605590
申请日：2003-10-10
申请人： Rama Divakaruni , Johnathan E. Faltermeier , Michael Maldei , Jay Strane
发明人： Rama Divakaruni , Johnathan E. Faltermeier , Michael Maldei , Jay Strane
IPC分类号： H01L21/60 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897
摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.
摘要翻译：提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。在槽中形成与基板和位线的位线接触。此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

10. 发明授权

US06790739B2 Structure and methods for process integration in vertical DRAM cell fabrication 有权
标题翻译：垂直DRAM单元制造过程集成的结构和方法
公开(公告)号：US06790739B2
公开(公告)日：2004-09-14
申请号：US10249997
申请日：2003-05-27
申请人： Rajeev Malik , Larry Nesbit , Jochen Beintner , Rama Divakaruni
发明人： Rajeev Malik , Larry Nesbit , Jochen Beintner , Rama Divakaruni
IPC分类号： H01L2120
CPC分类号： H01L27/10894 , H01L21/76224 , H01L27/10861
摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
摘要翻译：公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。然而，支撑区域中的初始衬垫氮化物材料仍然保持。然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

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