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1. 发明授权

US07100021B1 Barrier synchronization mechanism for processors of a systolic array 有权
标题翻译：收缩阵列处理器的屏障同步机制
公开(公告)号：US07100021B1
公开(公告)日：2006-08-29
申请号：US09978647
申请日：2001-10-16
申请人： John William Marshall , Barry S. Burns , Darren Kerr
发明人： John William Marshall , Barry S. Burns , Darren Kerr
IPC分类号： G06F9/22 , G06F9/52
CPC分类号： G06F9/52
摘要： A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronization mechanism that enables synchronization among processors of a column (i.e., different rows) of the systolic array. That is, the barrier synchronization function allows all participating processors within a column to reach a common point within their instruction code sequences before any of the processors proceed.
摘要翻译：一种机制在中间网络站中的处理引擎的处理器之间进行同步。处理引擎被配置为具有排列成行和列的多个处理器的收缩阵列。该机制包括能够使收缩阵列的列（即不同行）的处理器之间进行同步的障碍同步机制。也就是说，屏障同步功能允许列中的所有参与处理器在任何处理器进行之前到达其指令代码序列中的公共点。

2. 发明授权

US06986022B1 Boundary synchronization mechanism for a processor of a systolic array 有权
标题翻译：收缩阵列处理器的边界同步机制
公开(公告)号：US06986022B1
公开(公告)日：2006-01-10
申请号：US09978640
申请日：2001-10-16
申请人： John William Marshall , Barry S. Burns , Darren Kerr
发明人： John William Marshall , Barry S. Burns , Darren Kerr
IPC分类号： G06F15/80
CPC分类号： G06F15/8046
摘要： A mechanism synchronizes instruction code executing on a processor of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a boundary (temporal) synchronization mechanism for cycle-based synchronization within a processor of the array. The synchronization mechanism is generally implemented using specialized synchronization micro operation codes (“opcodes”).
摘要翻译：一种机制使在中间网络站中的处理引擎的处理器上执行的指令代码同步。处理引擎被配置为具有排列成行和列的多个处理器的收缩阵列。该机制包括用于阵列的处理器内的基于周期的同步的边界（时间）同步机制。同步机制通常使用专门的同步微操作代码（“操作码”）来实现。

3. 发明授权

US06920562B1 Tightly coupled software protocol decode with hardware data encryption 有权
标题翻译：紧密耦合的软件协议解码与硬件数据加密
公开(公告)号：US06920562B1
公开(公告)日：2005-07-19
申请号：US09216519
申请日：1998-12-18
申请人： Darren Kerr , John William Marshall
发明人： Darren Kerr , John William Marshall
IPC分类号： G06F9/30 , G06F9/38 , G06F21/00 , H04L9/00 , H04L29/06
CPC分类号： H04L63/0428 , G06F9/30003 , G06F9/3877 , G06F9/3885 , G06F9/3895 , G06F21/72
摘要： An encryption mechanism tightly-couples hardware data encryption functions with software-based protocol decode processing within a pipelined processor of a programmable processing engine. Tight-coupling is achieved by a micro-architecture of the pipelined processor that allows encryption functions to be accessed as a novel encryption execution unit of the processor. Such coupling substantially reduces the latency associated with conventional hardware/software interfaces.
摘要翻译：加密机制将硬件数据加密功能与可编程处理引擎的流水线处理器内的基于软件的协议解码处理紧密耦合。通过流水线处理器的微架构来实现紧耦合，其允许作为处理器的新型加密执行单元访问加密功能。这种耦合大大减少了与常规硬件/软件接口相关联的延迟。

4. 发明授权

US07139899B2 Selected register decode values for pipeline stage register addressing 有权
标题翻译：流水线级寄存器寻址的选定寄存器解码值
公开(公告)号：US07139899B2
公开(公告)日：2006-11-21
申请号：US09390079
申请日：1999-09-03
申请人： Darren Kerr , John William Marshall
发明人： Darren Kerr , John William Marshall
IPC分类号： G06F9/34
CPC分类号： G06F9/3826 , G06F9/3885
摘要： An instruction decode mechanism enables an instruction to control data flow bypassing hardware within a pipelined processor of a programmable processing engine. The control mechanism is defined by an instruction set of the processor as a unique register decode value that specifies either source operand bypassing (via a source bypass operand) or result bypassing (via a result bypass operand) from a previous instruction executing in pipeline stages of the processor. The source bypass operand allows source operand data to be shared among the parallel execution units of the pipelined processor, whereas the result bypass operand explicitly controls data flow within a pipeline of the processor through the use of result bypassing hardware of the processor. The instruction decode control mechanism essentially allows an instruction to directly identify a pipeline stage register for use as its source operand.
摘要翻译：指令解码机制使得能够控制在可编程处理引擎的流水线处理器内绕过硬件的数据流的指令。控制机制由处理器的指令集定义为唯一的寄存器解码值，其指定源操作数旁路（经由源旁路操作数）或结果绕过（通过结果旁路操作数）从前一条指令执行的流水线阶段处理器。源旁路操作数允许在流水线处理器的并行执行单元之间共享源操作数数据，而结果旁路操作数通过使用结果绕过处理器的硬件来明确地控制处理器流水线内的数据流。指令解码控制机制基本上允许指令直接识别流水线级寄存器以用作其源操作数。

5. 发明授权

US06965615B1 Packet striping across a parallel header processor 失效
标题翻译：数据包通过并行头处理器进行条带化
公开(公告)号：US06965615B1
公开(公告)日：2005-11-15
申请号：US09663777
申请日：2000-09-18
申请人： Darren Kerr , Jeffery Scott , John William Marshall , Scott Nellenbach
发明人： Darren Kerr , Jeffery Scott , John William Marshall , Scott Nellenbach
IPC分类号： H04J3/24 , H04L12/56
CPC分类号： H04L49/3072 , H04L49/25 , H04L49/3063
摘要： A technique is provided for striping packets across pipelines of a processing engine within a network switch. The processing engine comprises a plurality of processors arrayed as pipeline rows and columns embedded between input and output buffers of the engine. Each pipeline row or cluster includes a context memory having a plurality of window buffers of a defined size. Each packet is apportioned into fixed-sized contexts corresponding to the defined window size associated with each buffer of the context memory. The technique includes a mapping mechanism for correlating each context with a relative position within the packet, i.e., the beginning, middle and end contexts of a packet. The mapping mechanism facilitates reassembly of the packet at the output buffer, while obviating any any out-of-order issues involving the particular contexts of a packet.
摘要翻译：提供了一种技术，用于在网络交换机内的处理引擎的管道上分条分组。处理引擎包括多个处理器，其排列成嵌入在发动机的输入和输出缓冲器之间的管线行和列。每个管道行或群集包括具有多个定义大小的窗口缓冲器的上下文存储器。每个数据包被分配到与上下文存储器的每个缓冲器相关联的定义的窗口大小相对应的固定大小的上下文中。该技术包括用于将每个上下文与分组内的相对位置（即，分组的开始，中间和结束上下文）相关联的映射机制。映射机制有助于在输出缓冲器处重新组合分组，同时避免涉及分组的特定上下文的任何无序的问题。

6. 发明授权

US06804815B1 Sequence control mechanism for enabling out of order context processing 失效
标题翻译：用于启用无序上下文处理的序列控制机制
公开(公告)号：US06804815B1
公开(公告)日：2004-10-12
申请号：US09663775
申请日：2000-09-18
申请人： Darren Kerr , Jeffery B. Scott , John William Marshall , Kenneth H. Potter , Scott Nellenbach
发明人： Darren Kerr , Jeffery B. Scott , John William Marshall , Kenneth H. Potter , Scott Nellenbach
IPC分类号： G06F946
CPC分类号： H04L49/9094 , H04L49/90
摘要： A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.
摘要翻译：序列控制机制使具有排列为处理引擎的多个处理器的对称多处理器系统的处理器对上下文进行无序处理。引擎的处理器优选地被布置为嵌入在输入和输出缓冲器之间的多个行或群集，其中每个处理器群集被配置为以先进先出（FIFO）同步顺序处理上下文。然而，序列控制机制允许处理器群集之间的无序上下文处理，同时在需要的基础上选择性地执行这些簇之间的FIFO同步排序，即对某些上下文。结果，控制机制减少了这些处理器之间的不期望的处理延迟。

7. 发明授权

US06442669B2 Architecture for a process complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US06442669B2
公开(公告)日：2002-08-27
申请号：US09727068
申请日：2000-11-30
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

8. 发明授权

US07895412B1 Programmable arrayed processing engine architecture for a network switch 有权
标题翻译：用于网络交换机的可编程阵列处理引擎架构
公开(公告)号：US07895412B1
公开(公告)日：2011-02-22
申请号：US10184564
申请日：2002-06-27
申请人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
发明人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
IPC分类号： G06F15/80
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译：可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。

9. 发明授权

US07380101B2 Architecture for a processor complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US07380101B2
公开(公告)日：2008-05-27
申请号：US11023283
申请日：2004-12-27
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

10. 发明授权

US06272621B1 Synchronization and control system for an arrayed processing engine 有权
标题翻译：阵列处理引擎的同步和控制系统
公开(公告)号：US06272621B1
公开(公告)日：2001-08-07
申请号：US09642144
申请日：2000-08-18
申请人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
发明人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
摘要翻译：用于中间网络站的阵列处理引擎的同步和控制系统包括控制处理引擎的排序电路。处理引擎通常包括排列成并行管线的多个处理元件级。控制系统还包括输入头缓冲器（IHB）和输出头缓冲器（OHB），后者包括用于接收由管线处理的当前瞬态数据并用于解码控制信号以确定处理数据的目的地的电路。一个目的地是将OHB耦合到IHB的反馈路径，并将处理的数据返回到IHB，以便立即加载到可用管道中。

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