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1. 发明授权

US07290105B1 Zero overhead resource locks with attributes 有权
标题翻译：具有属性的零开销资源锁
公开(公告)号：US07290105B1
公开(公告)日：2007-10-30
申请号：US10320120
申请日：2002-12-16
申请人： Robert E. Jeter, Jr. , Kenneth H. Potter , Darren Kerr , John W. Marshall , Manish Changela
发明人： Robert E. Jeter, Jr. , Kenneth H. Potter , Darren Kerr , John W. Marshall , Manish Changela
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F2209/522 , G06F2209/523
摘要： A technique efficiently accesses locks associated with resources in a computer system. A processor accesses (e.g., acquires or releases) a lock by specifying and issuing a request to a resource controller, the request containing attribute and resource location information associated with the lock. In response, the resource controller applies the information contained in the request to an outstanding lock data structure to determine if the request should be blocked, blocked as a pending writer, allowed or an error condition. If the request is blocked, it remains blocked until the outstanding lock blocking the request is released. If the request is allowed, operations associated with the request are performed.
摘要翻译：技术有效地访问与计算机系统中的资源相关联的锁。处理器通过向资源控制器指定和发出请求来访问（例如，获取或释放）锁定，该请求包含与该锁相关联的属性和资源位置信息。作为响应，资源控制器将包含在请求中的信息应用于未完成的锁定数据结构，以确定请求是否应被阻止，被阻塞作为待决作者，允许或错误状况。如果请求被阻止，它将被阻止，直到释放阻塞请求的未锁定的锁。如果请求被允许，则执行与该请求相关联的操作。

2. 发明授权

US07139899B2 Selected register decode values for pipeline stage register addressing 有权
标题翻译：流水线级寄存器寻址的选定寄存器解码值
公开(公告)号：US07139899B2
公开(公告)日：2006-11-21
申请号：US09390079
申请日：1999-09-03
申请人： Darren Kerr , John William Marshall
发明人： Darren Kerr , John William Marshall
IPC分类号： G06F9/34
CPC分类号： G06F9/3826 , G06F9/3885
摘要： An instruction decode mechanism enables an instruction to control data flow bypassing hardware within a pipelined processor of a programmable processing engine. The control mechanism is defined by an instruction set of the processor as a unique register decode value that specifies either source operand bypassing (via a source bypass operand) or result bypassing (via a result bypass operand) from a previous instruction executing in pipeline stages of the processor. The source bypass operand allows source operand data to be shared among the parallel execution units of the pipelined processor, whereas the result bypass operand explicitly controls data flow within a pipeline of the processor through the use of result bypassing hardware of the processor. The instruction decode control mechanism essentially allows an instruction to directly identify a pipeline stage register for use as its source operand.
摘要翻译：指令解码机制使得能够控制在可编程处理引擎的流水线处理器内绕过硬件的数据流的指令。控制机制由处理器的指令集定义为唯一的寄存器解码值，其指定源操作数旁路（经由源旁路操作数）或结果绕过（通过结果旁路操作数）从前一条指令执行的流水线阶段处理器。源旁路操作数允许在流水线处理器的并行执行单元之间共享源操作数数据，而结果旁路操作数通过使用结果绕过处理器的硬件来明确地控制处理器流水线内的数据流。指令解码控制机制基本上允许指令直接识别流水线级寄存器以用作其源操作数。

3. 发明申请

US20050125643A1 Architecture for a processor complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US20050125643A1
公开(公告)日：2005-06-09
申请号：US11023283
申请日：2004-12-27
申请人： Michael Wright , Darren Kerr , Kenneth Key , William Jennings
发明人： Michael Wright , Darren Kerr , Kenneth Key , William Jennings
IPC分类号： G06F15/78 , G06F12/00
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

4. 发明申请

US20050027506A1 Method network flow switching and flow data export 有权
标题翻译：方法网络流量切换和流量数据导出
公开(公告)号：US20050027506A1
公开(公告)日：2005-02-03
申请号：US10924710
申请日：2004-08-23
申请人： Darren Kerr , Barry Bruins
发明人： Darren Kerr , Barry Bruins
IPC分类号： H04L12/56 , G06F9/455
CPC分类号： H04L45/00 , H04L45/566 , H04L47/2441 , Y10S707/99945 , Y10S707/99948
摘要： The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.
摘要翻译：本发明提供一种响应消息流模式切换网络的方法和系统。消息“流”被定义为包括要在特定源和特定目的地之间传送的一组分组。当网络中的路由器识别新的消息流时，它们确定该消息流中的数据包的适当处理，并缓存该消息流的信息。此后，当网络中的路由器识别作为该消息流的一部分的分组时，它们根据该消息流中的分组的适当处理来处理该分组。适当的处理可以包括确定用于路由那些分组的目的地端口以及确定访问控制是否允许将这些分组路由到其指示的目的地。

5. 发明授权

US06195739B1 Method and apparatus for passing data among processor complex stages of a pipelined processing engine 失效
标题翻译：用于在流水线处理引擎的处理器复杂级之间传递数据的方法和装置
公开(公告)号：US06195739B1
公开(公告)日：2001-02-27
申请号：US09106436
申请日：1998-06-29
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

6. 发明授权

US07895412B1 Programmable arrayed processing engine architecture for a network switch 有权
标题翻译：用于网络交换机的可编程阵列处理引擎架构
公开(公告)号：US07895412B1
公开(公告)日：2011-02-22
申请号：US10184564
申请日：2002-06-27
申请人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
发明人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
IPC分类号： G06F15/80
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译：可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。

7. 发明授权

US07380101B2 Architecture for a processor complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US07380101B2
公开(公告)日：2008-05-27
申请号：US11023283
申请日：2004-12-27
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

8. 发明授权

US06272621B1 Synchronization and control system for an arrayed processing engine 有权
标题翻译：阵列处理引擎的同步和控制系统
公开(公告)号：US06272621B1
公开(公告)日：2001-08-07
申请号：US09642144
申请日：2000-08-18
申请人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
发明人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
摘要翻译：用于中间网络站的阵列处理引擎的同步和控制系统包括控制处理引擎的排序电路。处理引擎通常包括排列成并行管线的多个处理元件级。控制系统还包括输入头缓冲器（IHB）和输出头缓冲器（OHB），后者包括用于接收由管线处理的当前瞬态数据并用于解码控制信号以确定处理数据的目的地的电路。一个目的地是将OHB耦合到IHB的反馈路径，并将处理的数据返回到IHB，以便立即加载到可用管道中。

9. 发明授权

US06173386B2 Parallel processor with debug capability 失效
标题翻译：具有调试功能的并行处理器
公开(公告)号：US06173386B2
公开(公告)日：2001-01-09
申请号：US09213291
申请日：1998-12-14
申请人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings , Scott Nellenbach
发明人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings , Scott Nellenbach
IPC分类号： G06F1516
CPC分类号： G06F11/3648
摘要： A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
摘要翻译：提供并行处理器，包括集成的调试功能。处理器包括流水线处理引擎，具有处理元件复杂级的阵列，以及输入和输出头缓冲器。提供了一种调试系统，当被触发时，可以将部分或全部处理元件复合体置于调试操作模式中。当复合体处于调试模式时，可能会发现复合体的组件电路的内部级的检查，以便于调试在处理器运行期间可能发生的软件和硬件错误。

10. 发明授权

US07100021B1 Barrier synchronization mechanism for processors of a systolic array 有权
标题翻译：收缩阵列处理器的屏障同步机制
公开(公告)号：US07100021B1
公开(公告)日：2006-08-29
申请号：US09978647
申请日：2001-10-16
申请人： John William Marshall , Barry S. Burns , Darren Kerr
发明人： John William Marshall , Barry S. Burns , Darren Kerr
IPC分类号： G06F9/22 , G06F9/52
CPC分类号： G06F9/52
摘要： A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronization mechanism that enables synchronization among processors of a column (i.e., different rows) of the systolic array. That is, the barrier synchronization function allows all participating processors within a column to reach a common point within their instruction code sequences before any of the processors proceed.
摘要翻译：一种机制在中间网络站中的处理引擎的处理器之间进行同步。处理引擎被配置为具有排列成行和列的多个处理器的收缩阵列。该机制包括能够使收缩阵列的列（即不同行）的处理器之间进行同步的障碍同步机制。也就是说，屏障同步功能允许列中的所有参与处理器在任何处理器进行之前到达其指令代码序列中的公共点。

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