专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07895412B1 Programmable arrayed processing engine architecture for a network switch 有权
标题翻译：用于网络交换机的可编程阵列处理引擎架构
公开(公告)号：US07895412B1
公开(公告)日：2011-02-22
申请号：US10184564
申请日：2002-06-27
申请人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
发明人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
IPC分类号： G06F15/80
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译：可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。

2. 发明授权

US07380101B2 Architecture for a processor complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US07380101B2
公开(公告)日：2008-05-27
申请号：US11023283
申请日：2004-12-27
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

3. 发明授权

US06681341B1 Processor isolation method for integrated multi-processor systems 失效
标题翻译：集成多处理器系统的处理器隔离方法
公开(公告)号：US06681341B1
公开(公告)日：2004-01-20
申请号：US09432526
申请日：1999-11-03
申请人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
发明人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
IPC分类号： G06F1100
CPC分类号： G06F11/2242
摘要： A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.
摘要翻译：处理器隔离技术在包含可编程阵列处理引擎的高度集成的多处理器电路中增强了调试能力，用于有效地处理计算机网络的中间网络站内的瞬态数据。该技术包括一种用于使用可经由耦合到发动机的远程处理器的带外总线访问的寄存器组来对处理器复合体的每个处理器进行编码入口点的机制。可编程入口点机制与旁路能力相结合，该旁路能力通过不起作用或以其他方式不能处理数据的处理器复合体传递瞬态数据。调试技术的另一方面涉及覆盖由每个处理器复合体提供的完成控制信号以提升处理引擎的流水线的能力。

4. 发明授权

US06385747B1 Testing of replicated components of electronic device 有权
标题翻译：测试电子设备的复制组件
公开(公告)号：US06385747B1
公开(公告)日：2002-05-07
申请号：US09212314
申请日：1998-12-14
申请人： Jeffery Burl Scott , Kenneth Michael Key , Michael L. Wright , Scott Nellenbach
发明人： Jeffery Burl Scott , Kenneth Michael Key , Michael L. Wright , Scott Nellenbach
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C29/40
摘要： A technique is provided for use in testing replicated components (e.g., identical circuit components) of an electronic device for defects. In one aspect of this testing technique, the same test inputs may be broadcast, in parallel, from a single test interface to each of the replicated components of the electronic device under test. Respective test outputs generated by the replicated components in response to the test inputs may be supplied to a comparator, comprised in the electronic device, that compares the respective test outputs to each other and generates a fault signal if corresponding test outputs are not identical. This fault signal may be supplied to an external test interface pin of the single test interface, and its assertion may indicate that one or more of the replicated components may be defective. The respective test outputs may be multiplexed to permit output via an external interface of respective test outputs from a selected component. These respective test outputs may be compared to expected values therefor whereby to determine presence and/or nature of defects in the replicated components.
摘要翻译：提供了用于测试用于缺陷的电子设备的复制组件（例如，相同的电路组件）的技术。在该测试技术的一个方面，相同的测试输入可以并行地从单个测试接口广播到被测试的电子设备的每个复制组件。响应于测试输入而由复制组件生成的各个测试输出可以被提供给包括在电子设备中的比较器，其将相应的测试输出彼此进行比较，并且如果相应的测试输出不相同则产生故障信号。该故障信号可以被提供给单个测试接口的外部测试接口引脚，并且其断言可以指示一个或多个复制部件可能是有缺陷的。相应的测试输出可以被多路复用以允许经由所选择的组件的相应测试输出的外部接口的输出。这些各自的测试输出可以与期望值进行比较，从而确定复制组件中的缺陷的存在和/或性质。

5. 发明授权

US06272621B1 Synchronization and control system for an arrayed processing engine 有权
标题翻译：阵列处理引擎的同步和控制系统
公开(公告)号：US06272621B1
公开(公告)日：2001-08-07
申请号：US09642144
申请日：2000-08-18
申请人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
发明人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
摘要翻译：用于中间网络站的阵列处理引擎的同步和控制系统包括控制处理引擎的排序电路。处理引擎通常包括排列成并行管线的多个处理元件级。控制系统还包括输入头缓冲器（IHB）和输出头缓冲器（OHB），后者包括用于接收由管线处理的当前瞬态数据并用于解码控制信号以确定处理数据的目的地的电路。一个目的地是将OHB耦合到IHB的反馈路径，并将处理的数据返回到IHB，以便立即加载到可用管道中。

6. 发明授权

US06173386B2 Parallel processor with debug capability 失效
标题翻译：具有调试功能的并行处理器
公开(公告)号：US06173386B2
公开(公告)日：2001-01-09
申请号：US09213291
申请日：1998-12-14
申请人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings , Scott Nellenbach
发明人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings , Scott Nellenbach
IPC分类号： G06F1516
CPC分类号： G06F11/3648
摘要： A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
摘要翻译：提供并行处理器，包括集成的调试功能。处理器包括流水线处理引擎，具有处理元件复杂级的阵列，以及输入和输出头缓冲器。提供了一种调试系统，当被触发时，可以将部分或全部处理元件复合体置于调试操作模式中。当复合体处于调试模式时，可能会发现复合体的组件电路的内部级的检查，以便于调试在处理器运行期间可能发生的软件和硬件错误。

7. 发明授权

US4797332A Method of preparing ceramic surfaces for wetting thereof by alkali metals 失效
标题翻译：制备用碱金属润湿陶瓷表面的方法
公开(公告)号：US4797332A
公开(公告)日：1989-01-10
申请号：US97521
申请日：1987-09-16
申请人： Peter Barrow , Michael L. Wright
发明人： Peter Barrow , Michael L. Wright
IPC分类号： C04B41/80 , C04B35/113 , C04B41/50 , C04B41/85 , C04B41/87 , H01M10/24 , H01M10/39
CPC分类号： C04B41/009 , C04B35/113 , C04B41/50 , C04B41/5025 , C04B41/85 , C04B41/87 , H01M10/3927
摘要： The invention provides a method of preparing a surface of a ceramic solid electrolyte conductor of alkali metal ions for wetting by said alkali metal in molten form. The method comprises doping the ceramic surface with an oxide of a transition metal. Transition metals such as Fe, Ni, Cu, Mn, Co, Cr or Mo have suitable oxides for doping beta-alumina for wetting by sodium.
摘要翻译：本发明提供一种制备碱金属离子的陶瓷固体电解质导体的表面的方法，用于使所述碱金属以熔融形式润湿。该方法包括用过渡金属的氧化物掺杂陶瓷表面。过渡金属如Fe，Ni，Cu，Mn，Co，Cr或Mo具有合适的氧化物，用于掺杂β-氧化铝用于润湿钠。

8. 发明授权

US4529676A Electrochemical cell 失效
标题翻译：电化学电池
公开(公告)号：US4529676A
公开(公告)日：1985-07-16
申请号：US612656
申请日：1984-05-21
申请人： Roy C. Galloway , Roger J. Bones , David A. Teagle , Michael L. Wright
发明人： Roy C. Galloway , Roger J. Bones , David A. Teagle , Michael L. Wright
IPC分类号： H01M4/02 , H01M10/39 , H01M4/36
CPC分类号： H01M4/02 , H01M10/39 , Y10T29/49108
摘要： The invention provides a method of making a cathode for an electrochemical cell which involves incorporating sodium chloride in dispersed form into an electrolyte permeable matrix and impregnating the matrix with a suitable sodium aluminum halide molten salt electrolyte. The matrix is formed from a transition metal selected from at least one member of the group consisting of Fe, Ni, Co, Cr and Mn, and the intermediate refractory hard metal compounds of said transition metals with at least one non-metal selected from the group consisting of carbon, silicon, boron, nitrogen and phosphorus.
摘要翻译：本发明提供一种制备用于电化学电池的阴极的方法，其涉及将分散形式的氯化钠掺入到电解质渗透性基质中，并用合适的铝酸钠熔融盐电解质浸渍该基体。所述基质由选自Fe，Ni，Co，Cr和Mn中的至少一种成员的过渡金属形成，所述过渡金属的中间耐火硬金属化合物与至少一种非金属选自由碳，硅，硼，氮和磷组成的组。

9. 发明授权

US4348468A Beta alumina solid electrolyte material and its manufacture and electrochemical cells or other energy conversion devices containing such material 失效
标题翻译： β氧化铝固体电解质材料及其制造和电化学电池或其他含有这种材料的能量转换装置
公开(公告)号：US4348468A
公开(公告)日：1982-09-07
申请号：US217333
申请日：1980-12-17
申请人： Michael L. Wright
发明人： Michael L. Wright
IPC分类号： C01F7/02 , H01B1/08 , H01M10/39
CPC分类号： H01M10/3909
摘要： In a sodium sulphur cell or other electrochemical cell or energy conversion device in which beta-alumina is used as a solid electrolyte in contact with liquid sodium, improved wetting of the electrolyte by the sodium is obtained by coating the electrolyte, on the surface in contact with the sodium, with a metal, such as lead or bismuth, which will form an alloy with sodium. Conveniently the electrolyte is coated with an aqueous solution of lead acetate, dried and the lead acetate decomposed by heating to leave a lead coating.
摘要翻译：在其中使用β-氧化铝作为与液态钠接触的固体电解质的钠硫电池或其他电化学电池或能量转换装置中，通过在接触的表面上涂覆电解质来获得电解质通过钠的改善的润湿与钠，与金属，如铅或铋，将与钠形成合金。方便地，电解质被乙酸铅水溶液包覆，干燥，乙酸铅通过加热分解，留下铅涂层。

10. 发明授权

US08603629B2 Flashing and waterproofing membrane 有权
标题翻译：闪光防水膜
公开(公告)号：US08603629B2
公开(公告)日：2013-12-10
申请号：US12581222
申请日：2009-10-19
申请人： Robert S. Simpson , Michael L. Wright , Whitney J. Croft
发明人： Robert S. Simpson , Michael L. Wright , Whitney J. Croft
IPC分类号： B32B33/00 , B32B37/02 , B32B37/14 , B32B3/10
CPC分类号： E04B1/6803 , B32B37/02 , B32B37/08 , B32B2037/243 , B32B2037/268 , B32B2309/105 , B32B2318/00 , E04B1/66 , E04D5/10 , E04D5/12 , Y10T156/10 , Y10T428/141 , Y10T428/24322 , Y10T428/24967 , Y10T428/26 , Y10T428/263 , Y10T428/28
摘要： A laminate tape that has a bottom layer of aggressive adhesive formulated to have sufficient adhesion to construction materials to as low as 20 degrees F. The adhesive is applied in a layer of about 2 to 5 mils. A second layer that is about 10 to 60 mils thick is made of rubberized asphalt, which provides self-sealing capabilities. In one embodiment, the first layer has strips of adhesive and sections of rubberized asphalt. The third layer is a film, which can be a thin, contiguous polymer, fabric or particulate. The laminate can be used where a strong adhesive is needed that will adhere to construction materials at or near 20 degrees Fahrenheit, while still retaining self-sealing characteristics.
摘要翻译：具有防腐粘合剂底层的层压带，其被配制为具有足够的粘合性至建筑材料至低至20华氏度。粘合剂以约2至5密耳的层施加。约10至60密耳厚的第二层由橡胶沥青制成，其提供自密封性能。在一个实施例中，第一层具有胶粘带和橡胶沥青的部分。第三层是膜，其可以是薄的，连续的聚合物，织物或颗粒。该层压板可用于需要强粘合剂的地方，该强粘合剂将粘附在20华氏度或接近20华氏度的建筑材料上，同时仍然保持自密封特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式