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1. 发明授权

US06836831B2 Independent sequencers in a DRAM control structure 失效
标题翻译： DRAM控制结构中的独立定序器
公开(公告)号：US06836831B2
公开(公告)日：2004-12-28
申请号：US10215404
申请日：2002-08-08
申请人： John Michael Borkenhagen , Robert Allen Drehmel , Brian T. Vanderpool
发明人： John Michael Borkenhagen , Robert Allen Drehmel , Brian T. Vanderpool
IPC分类号： G06F1316
CPC分类号： G06F13/1647
摘要： Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.
摘要翻译：公开了一种用于提供存储器控制器的计算机系统中的方法和装置，其特征在于存储器系统中的每个存储器组的专用库定序器。每个银行定序器控制负载分配和存储请求到中央控制器，使得发送到中央控制器的每个请求可以在中央控制器接收请求时由相关联的存储体来服务。由于中央控制器接收到的每个请求都是从银行定时的角度来看是有效的，所以中央控制器可以自由地处理来自预定优先级的请求，而不用担心银行的可用性。这显着地改善了处理系统中存储器控制器的设计。

2. 发明授权

US07577793B2 Patrol snooping for higher level cache eviction candidate identification 失效
标题翻译：巡逻窥探高级缓存驱逐候选人识别
公开(公告)号：US07577793B2
公开(公告)日：2009-08-18
申请号：US11335765
申请日：2006-01-19
申请人： John Michael Borkenhagen , Brian T. Vanderpool
发明人： John Michael Borkenhagen , Brian T. Vanderpool
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/128 , G06F12/0897
摘要： A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.
摘要翻译：具有巡逻窥探音序器的计算机系统，其通过保持在较高级别高速缓存中的高速缓存行的地址进行排序，使得使用这些地址进行窥探读取到较低级别的高速缓存。如果保持在较高级别高速缓存中的特定高速缓存行不被保持在较低级高速缓存中，则当新的高速缓存行必须被加载到更高级高速缓存中时，特定高速缓存行被标识为较高级高速缓存中的逐出候选。

3. 发明授权

US06754858B2 SDRAM address error detection method and apparatus 失效
标题翻译： SDRAM地址错误检测方法和装置
公开(公告)号：US06754858B2
公开(公告)日：2004-06-22
申请号：US09820436
申请日：2001-03-29
申请人： John Michael Borkenhagen , Brian T. Vanderpool
发明人： John Michael Borkenhagen , Brian T. Vanderpool
IPC分类号： G11C2900
CPC分类号： G11C11/408 , G11C7/24
摘要： Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.
摘要翻译：提供同步动态随机存取存储器（SDRAM）方法和装置，用于实现地址错误检测。在存储器接口上检测到寻址错误，独立于数据ECC，具有减少的存储器读访问延迟和改进的处理器性能。检测到寻址错误，同时允许区分停止系统所需的存储器寻址故障和允许继续操作的存储器单元故障。为SDRAM的写突发生成预定义的模式。预定义模式取决于写入地址。在写入突发的每次突发传送到SDRAM时，预定义模式的一部分被顺序地存储到SDRAM中。从读取脉冲串的读取地址产生预期模式。在读突发期间检索存储的预定义模式。将检索到的预定义模式与生成的期望模式进行比较，以识别寻址错误的类型。

4. 发明授权

US07865757B2 Capacity on demand using signaling bus control 有权
标题翻译：使用信号总线控制的按需容量
公开(公告)号：US07865757B2
公开(公告)日：2011-01-04
申请号：US12018359
申请日：2008-01-23
申请人： John Michael Borkenhagen , Benjamin F. Carter, III , Stephen Roland Levesque
发明人： John Michael Borkenhagen , Benjamin F. Carter, III , Stephen Roland Levesque
IPC分类号： G06F1/00 , G06F1/04
CPC分类号： G06F9/5061
摘要： An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.
摘要翻译：公开了一种用于通过使用控制改变计算机系统中的信令总线上的延迟和/或带宽来提供按需容量的装置和方法。如果需要额外的容量，则需要授权额外的容量。如果被授权，增加信令总线的带宽以在计算系统中提供额外的容量。或者，经授权，减少了通过信令总线的数据传输的延迟。在另一个替代方案中，经过授权，调整存储器定时以加速存储器获取和存储。

5. 发明授权

US07707463B2 Implementing directory organization to selectively optimize performance or reliability 有权
标题翻译：实施目录组织以选择性地优化性能或可靠性
公开(公告)号：US07707463B2
公开(公告)日：2010-04-27
申请号：US11290894
申请日：2005-11-30
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G06F12/082
摘要： A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.
摘要翻译：提供了一种用于实现目录组织以选择性地优化计算机系统中的性能或可靠性的方法和装置。目录包括用户选择的操作模式，包括演奏模式和可靠性模式。在可靠性模式下，更多的目录位用于纠错和检测。在性能模式下，不用于纠错和检测的回收目录位用于更多的关联性。

6. 发明申请

US20090164990A1 Apparatus for and Method for Real-Time Optimization of virtual Machine Input/Output Performance 有权
标题翻译：虚拟机输入/输出性能实时优化设备及方法
公开(公告)号：US20090164990A1
公开(公告)日：2009-06-25
申请号：US11959473
申请日：2007-12-19
申请人： Shmuel Ben-Yehuda , John Michael Borkenhagen
发明人： Shmuel Ben-Yehuda , John Michael Borkenhagen
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/545 , G06F9/45558 , G06F2009/45579
摘要： The present invention implements a mechanism to decide when it is beneficial to switch from the current virtual input/output mechanism to a different one. The present invention determines which input/output mechanism each virtual machine should use based on the available input/output resources of the virtual machines (with their respective available input/output adapters), the number of virtual machines running and their input/output needs, and the input/output needs of the virtual machine being considered. The present invention also provides a mechanism for virtual machine to seamlessly switch input/output mechanisms. When beneficial, the standard hot-plug mechanism of the virtual machine and the hypervisor is used to first remove the existing input/output mechanism and then add the new input/output mechanism.
摘要翻译：本发明实现了一种机制，用于决定什么时候从当前的虚拟输入/输出机制切换到不同的虚拟输入/输出机制是有益的。本发明基于虚拟机（其各自的可用输入/输出适配器）的可用输入/输出资源，运行的虚拟机的数量及其输入/输出需求来确定每个虚拟机应该使用哪个输入/输出机制，并考虑虚拟机的输入/输出需求。本发明还提供了一种用于虚拟机无缝切换输入/输出机制的机制。有利的是，使用虚拟机和管理程序的标准热插拔机制来首先删除现有的输入/输出机制，然后添加新的输入/输出机制。

7. 发明授权

US07526692B2 Diagnostic interface architecture for memory device 有权
标题翻译：内存设备的诊断接口架构
公开(公告)号：US07526692B2
公开(公告)日：2009-04-28
申请号：US10955735
申请日：2004-09-30
申请人： John Michael Borkenhagen , William Paul Hovis , James Anthony Marcella , Paul Rudrud
发明人： John Michael Borkenhagen , William Paul Hovis , James Anthony Marcella , Paul Rudrud
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5602
摘要： A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.
摘要翻译：用于存储器设备的诊断接口架构在一个方面支持通常与从存储器件读取数据和/或将数据写入存储器件一起使用的一个或多个动态可重新配置的功能互连。动态可重构功能互连能够被配置为以功能或诊断模式操作，由此在诊断模式中，这种互连可以用于传送诊断信息以支持一个或多个诊断操作。诊断接口架构还可以支持给定存储器设备中的多个诊断接口，其中至少一个这样的诊断接口能够响应于另一诊断接口中的故障被选择性地启用。

8. 发明授权

US07392418B2 Capacity on demand using signaling bus control 有权
标题翻译：使用信号总线控制的按需容量
公开(公告)号：US07392418B2
公开(公告)日：2008-06-24
申请号：US11016204
申请日：2004-12-17
申请人： John Michael Borkenhagen , Benjamin F. Carter, III , Stephen Roland Levesque
发明人： John Michael Borkenhagen , Benjamin F. Carter, III , Stephen Roland Levesque
IPC分类号： G06F1/00 , G06F1/04 , G06F1/14
CPC分类号： G06F9/5061
摘要： An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.
摘要翻译：公开了一种用于通过使用控制改变计算机系统中的信令总线上的延迟和/或带宽来提供按需容量的装置和方法。如果需要额外的容量，则需要授权额外的容量。如果被授权，增加信令总线的带宽以在计算系统中提供额外的容量。或者，经授权，减少了通过信令总线的数据传输的延迟。在另一个替代方案中，经过授权，调整存储器定时以加速存储器获取和存储。

9. 发明授权

US07334070B2 Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels 失效
标题翻译：多通道存储器结构，用于在存储器通道之间桥接的节点的菊花链式布置
公开(公告)号：US07334070B2
公开(公告)日：2008-02-19
申请号：US10977770
申请日：2004-10-29
申请人： John Michael Borkenhagen
发明人： John Michael Borkenhagen
IPC分类号： G06F13/00 , G06F15/16 , H04J1/16
CPC分类号： G06F13/1673 , G06F13/1684
摘要： Multiple memory channels of a multi-channel memory architecture are effectively bridged together to enable data traffic associated with various nodes in daisy chain arrangement to be communicated over both memory channels. For example, a daisy chain arrangement of nodes, such as FB-DIMM memory modules disposed in a first memory channel may be coupled to a second memory channel, with support for communicating data associated with one of the nodes over either or both of the first and second memory channels.
摘要翻译：多通道存储器架构的多个存储器通道被有效地桥接在一起，以使与菊花链布置中的各种节点相关联的数据流量能够通过两个存储器通道进行通信。例如，布置在第一存储器通道中的诸如FB-DIMM存储器模块的节点的菊花链布置可以耦合到第二存储器通道，支持通过第一存储器通道中的任一个或两者的通信数据相关联的节点和第二存储器通道。

10. 发明申请

US20080028125A1 Computer System Having an Apportionable Data Bus 有权
标题翻译：具有可分配数据总线的计算机系统
公开(公告)号：US20080028125A1
公开(公告)日：2008-01-31
申请号：US11459955
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F12/00
CPC分类号： G06F13/1678 , G06F13/1684
摘要： A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.
摘要翻译：具有耦合存储器控制器和存储器的数据总线的存储器系统。数据总线具有多个数据总线位。数据总线可编程地分配给专用于从存储器控制器向存储器发送数据的第一部分和专用于将数据从存储器传送到存储器控制器的第二部分。分配可以通过将存储器中的存储器芯片上的引脚适当地连接到存储器控制器到逻辑值来分配。或者，可以在释放时间的情况下将分配扫描到存储器控制器和存储器中。在另一替代方案中，可以通过暂停数据传送和动态地改变第一部分和第二部分的大小来改变分配。

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