专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06519843B2 Method of forming a chip carrier by joining a laminate layer and stiffener 失效
标题翻译：通过接合层压层和加强件形成芯片载体的方法
公开(公告)号：US06519843B2
公开(公告)日：2003-02-18
申请号：US09772418
申请日：2001-01-30
申请人： John M. Lauffer , Heike Marcello , David J. Russell
发明人： John M. Lauffer , Heike Marcello , David J. Russell
IPC分类号： H05K334
CPC分类号： H05K3/0061 , H01L21/4803 , H01L23/36 , H01L2924/0002 , H05K1/183 , H05K3/0023 , H05K3/386 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/49155 , Y10T29/53178 , Y10T156/1798 , H01L2924/00
摘要： A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge. As a result, a semiconductor component can be flush mounted in the cavity with optimal thermal conductivity to the metal stiffener.
摘要翻译：腔型芯片模块。该模块形成有介于金属加强件和层压顶层之间的可光成像材料的粘合剂接合层，中间孔限定在顶层中。可光成像材料暴露于光化辐射，除了与顶层中的孔相对应的区域之外。可光成像材料的未曝光区域被开发出来以在接合层中形成窗口。将顶层，接合层和加强件层压在一起，窗口和孔对齐，并且加强件的一部分跨越孔以在所得到的基底中限定空腔。未曝光的可光成像材料的去除以及将接合层选择性地暴露于光化辐射，保持空腔不含可光成像的材料并且抑制可光成像材料从其内边缘渗入空腔。结果，半导体部件可以齐平地安装在空腔中，对金属加强件具有最佳的导热性。

2. 发明授权

US06195264B1 Laminate substrate having joining layer of photoimageable material 失效
标题翻译：具有可光成像材料接合层的层叠基板
公开(公告)号：US06195264B1
公开(公告)日：2001-02-27
申请号：US09195389
申请日：1998-11-18
申请人： John M. Lauffer , Heike Marcello , David J. Russell
发明人： John M. Lauffer , Heike Marcello , David J. Russell
IPC分类号： H05K118
CPC分类号： H05K3/0061 , H01L21/4803 , H01L23/36 , H01L2924/0002 , H05K1/183 , H05K3/0023 , H05K3/386 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/49155 , Y10T29/53178 , Y10T156/1798 , H01L2924/00
摘要： A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge. As a result, a semiconductor component can be flush mounted in the cavity with optimal thermal conductivity to the metal stiffener.
摘要翻译：腔型芯片模块。该模块形成有介于金属加强件和层压顶层之间的可光成像材料的粘合剂接合层，中间孔限定在顶层中。光致成像材料暴露于光化辐射，除了对应于顶层中的孔的区域外。可光成像材料的未曝光区域被开发出来以在接合层中形成窗口。将顶层，接合层和加强件层压在一起，窗口和孔对齐，并且加强件的一部分跨越孔以在所得到的基底中限定空腔。未曝光的可光成像材料的去除以及将接合层选择性地暴露于光化辐射，保持空腔不含可光成像的材料并且抑制可光成像材料从其内边缘渗入空腔。结果，半导体部件可以齐平地安装在空腔中，对金属加强件具有最佳的导热性。

3. 发明授权

US06521844B1 Through hole in a photoimageable dielectric structure with wired and uncured dielectric 失效
标题翻译：透光电介质结构中的通孔，有线和未固化电介质
公开(公告)号：US06521844B1
公开(公告)日：2003-02-18
申请号：US09430076
申请日：1999-10-29
申请人： Stephen J. Fuerniss , Gary Johansson , Ross W. Keesler , John M. Lauffer , Voya R. Markovich , Peter A. Moschak , David J. Russell , William E. Wilson
发明人： Stephen J. Fuerniss , Gary Johansson , Ross W. Keesler , John M. Lauffer , Voya R. Markovich , Peter A. Moschak , David J. Russell , William E. Wilson
IPC分类号： H05K100
CPC分类号： H05K3/0023 , H05K1/056 , H05K3/445 , H05K3/4641 , H05K2203/1476 , Y10T29/49165
摘要： An electronic structure. The electronic structure comprises a layer. The layer includes: a cylindrical volume; a fully cured annular volume of a photoimageable dielectric (PID) material circumscribing the cylindrical volume; and a partially cured remaining volume of the PID material circumscribing the annular volume. The cylindrical volume may include a via. The structure can include a power plane.
摘要翻译：电子结构。电子结构包括一层。该层包括：圆柱体积; 完全固化的圆环体积的环绕光学成像的电介质（PID）材料; 以及围绕环形体积的PID材料的部分固化的剩余容积。圆柱体积可以包括通孔。该结构可以包括电力平面。

4. 发明授权

US06391210B2 Process for manufacturing a multi-layer circuit board 失效
标题翻译：制造多层电路板的工艺
公开(公告)号：US06391210B2
公开(公告)日：2002-05-21
申请号：US09901848
申请日：2001-07-09
申请人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
发明人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
IPC分类号： H01B1300
CPC分类号： H05K3/4652 , H05K3/0023 , H05K3/0035 , H05K2203/0508 , H05K2203/0554
摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.
摘要翻译：一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

5. 发明授权

US06689543B2 Laser ablatable material and its use 失效
标题翻译：激光可烧蚀材料及其用途
公开(公告)号：US06689543B2
公开(公告)日：2004-02-10
申请号：US10073558
申请日：2002-02-11
申请人： John S. Kresge , John M. Lauffer , David J. Russell
发明人： John S. Kresge , John M. Lauffer , David J. Russell
IPC分类号： G03C556
CPC分类号： H05K3/0032 , B23K2103/42 , B23K2103/50 , B41M5/24 , H05K1/0326 , H05K1/0373 , H05K2201/0112 , Y10S430/146
摘要： An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.
摘要翻译：通过向树脂中添加染料或染料，在用于激光烧蚀树脂的激光器的发射波长处具有显着的能量吸收，提供了表现出良好的激光烧蚀和对衬底的良好粘合性的环氧树脂。将含有染料或染料的树脂涂覆在基材上并固化，或在固化条件下层压到基材上。通过激光烧蚀在所述固化膜中形成所需的开口。这允许使用最佳技术来形成微通孔。

6. 发明授权

US06423905B1 Printed wiring board with improved plated through hole fatigue life 有权
标题翻译：印刷电路板，具有改善的电镀通孔疲劳寿命
公开(公告)号：US06423905B1
公开(公告)日：2002-07-23
申请号：US09562109
申请日：2000-05-01
申请人： William L. Brodsky , Kevin T. Knadle , John M. Lauffer , Douglas O. Powell , David J. Russell
发明人： William L. Brodsky , Kevin T. Knadle , John M. Lauffer , Douglas O. Powell , David J. Russell
IPC分类号： H05K103
CPC分类号： H05K3/4688 , H05K1/0271 , H05K3/429 , H05K2201/0133 , H05K2201/0195
摘要： A printed wiring board having a layered composite of metal planes and dielectric layers. At least one of the dielectric layers has a modulus lower than the modulus of the remaining dielectric material layers. A plating, extending through the layered composite, has a first land on a first external surface of the layered composite, a second land on a second external surface of the layered composite, and a barrel extending between the first land and the second land. The lower modulus dielectric material layer deforms during thermal excursions of the printed wiring board in such a way as to reduce the strains imposed on both the lands and the barrel of the plated through holes.
摘要翻译：一种具有金属平面和电介质层的复合层的印刷电路板。电介质层中的至少一个具有低于剩余介电材料层的模量的模量。延伸穿过层状复合材料的电镀具有在层状复合材料的第一外表面上的第一焊盘，层状复合材料的第二外表面上的第二焊盘，以及在第一焊盘和第二焊盘之间延伸的镜筒。在印刷线路板的热偏移期间，较低模量的介电材料层变形，以便减小施加在电镀通孔的焊盘和圆筒上的应变。

7. 发明授权

US06361923B1 Laser ablatable material and its use 失效
公开(公告)号：US06361923B1
公开(公告)日：2002-03-26
申请号：US09375957
申请日：1999-08-17
申请人： John S. Kresge , John M. Lauffer , David J. Russell
发明人： John S. Kresge , John M. Lauffer , David J. Russell
IPC分类号： G03C173
CPC分类号： H05K3/0032 , B23K2103/42 , B23K2103/50 , B41M5/24 , H05K1/0326 , H05K1/0373 , H05K2201/0112 , Y10S430/146
摘要： An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.

8. 发明授权

US06830875B2 Forming a through hole in a photoimageable dielectric structure 失效
标题翻译：在可光成像的电介质结构中形成通孔
公开(公告)号：US06830875B2
公开(公告)日：2004-12-14
申请号：US10266020
申请日：2002-10-07
申请人： Stephen J. Fuerniss , Gary Johansson , Ross W. Keesler , John M. Lauffer , Voya R. Markovich , Peter A. Moschak , David J. Russell , William E. Wilson
发明人： Stephen J. Fuerniss , Gary Johansson , Ross W. Keesler , John M. Lauffer , Voya R. Markovich , Peter A. Moschak , David J. Russell , William E. Wilson
IPC分类号： G03F700
CPC分类号： H05K3/0023 , H05K1/056 , H05K3/445 , H05K3/4641 , H05K2203/1476 , Y10T29/49165
摘要： A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.
摘要翻译：一种形成电子结构的方法。提供是包括可光成像电介质（PID）材料的圆柱体积，围绕圆柱体积的PID材料的环形体积以及围绕环形体积的PID材料的剩余体积的层。该层被光刻地暴露于辐射。环形体积被辐射完全固化。剩余体积由所述辐射的剩余体积部分固化。该方法防止圆柱体积的固化，其中圆柱体积中的PID材料保持未固化。

9. 发明授权

US6080668A Sequential build-up organic chip carrier and method of manufacture 失效
标题翻译：顺序构建有机芯片载体及其制造方法
公开(公告)号：US6080668A
公开(公告)日：2000-06-27
申请号：US58266
申请日：1998-04-10
申请人： John M. Lauffer , David J. Russell
发明人： John M. Lauffer , David J. Russell
IPC分类号： H01L21/48 , H01L23/498 , H05K3/00 , H05K3/28 , H05K3/40 , H05K3/46 , H01L21/44
CPC分类号： H05K3/0023 , H01L21/4857 , H01L23/49894 , H05K3/4614 , H01L2924/0002 , H05K2201/0355 , H05K2201/09481 , H05K2201/09509 , H05K2201/0959 , H05K3/0094 , H05K3/28 , H05K3/4069 , H05K3/4652
摘要： A method for manufacturing electronic circuit assemblies. A layer of dielectric material is attached to a layer of electrically conductive material. Vias are formed in the layer of dielectric material and filled with conductive paste material. The resulting assembly is attached to a substrate. Because the vias are formed and filled before the dielectric layer is attached to the substrate, it is not necessary to scrap the entire multi-layer structure, which includes the substrate and all the attached layers, when a problem occurs during via formation or filling. This increases the overall yield for the entire circuit assembly manufacturing process.
摘要翻译：一种用于制造电子电路组件的方法。电介质材料层附着在导电材料层上。通孔形成在电介质材料层中并填充有导电糊材料。所得到的组件附接到基底。由于在介电层附着到基板之前形成和填充通孔，所以当通孔形成或填充期间出现问题时，不需要废除包括基板和所有附着层在内的整个多层结构。这增加了整个电路组件制造过程的总产量。

10. 发明授权

US06542379B1 Circuitry with integrated passive components and method for producing 有权
标题翻译：集成无源元件的电路和生产方法
公开(公告)号：US06542379B1
公开(公告)日：2003-04-01
申请号：US09353992
申请日：1999-07-15
申请人： John M. Lauffer , David J. Russell
发明人： John M. Lauffer , David J. Russell
IPC分类号： H05K116
CPC分类号： H01F41/041 , H01F17/0033 , H05K1/095 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/0023 , H05K3/386 , H05K3/4069 , H05K3/4644 , H05K2201/0187 , H05K2201/0191 , H05K2201/0209 , H05K2201/0367 , H05K2201/086 , H05K2201/09563 , H05K2201/097 , H05K2201/09881 , H05K2203/0568 , H05K2203/1453 , H05K2203/1461 , Y10T29/4913 , Y10T29/49155 , Y10T29/49169 , Y10T428/24917 , Y10T428/2495 , Y10T428/24967 , Y10T428/24975
摘要： Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated in to electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material. The dielectric is photoimaged and etched to provide one or more recesses or openings for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric is described as well as the method of manufacturing the same.
摘要翻译：电容器，电阻器，电感器，变压器，滤波器和谐振器等被动电气元件集成到电路中，利用最大限度地利用衬底的平面来进行高密度放置有源元件例如逻辑或存储器集成电路。将无源部件集成到利用可光成像的电介质材料的常规电路板中。电介质被光刻和蚀刻以提供用于无源器件的一个或多个凹部或开口，以及互连集成电路板的输入和输出的光电隔离。描述了包括集成到光电介质中的无源器件中的至少一个的电子结构及其制造方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式