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1. 发明授权

US4494004A Electron beam system 失效
标题翻译：电子束系统
公开(公告)号：US4494004A
公开(公告)日：1985-01-15
申请号：US510385
申请日：1983-07-01
申请人： John L. Mauer, IV , Michel S. Michail , Ollie C. Woodard
发明人： John L. Mauer, IV , Michel S. Michail , Ollie C. Woodard
IPC分类号： H01J37/147 , H01J37/317 , H01J37/302
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/1474 , H01J37/3174 , H01J2237/30488 , H01J2237/30494 , H01J2237/31764
摘要： An electron beam method and apparatus, for writing patterns, such as on semiconductor wafers, in which the writing field is divided into a large number of overlapping subfields with a predetermined periodicity. Subfield to subfield moves are made in a stepped sequential scan, such as raster, while patterns, within a subfield, are addressed using vector scan and written using a sequential scan. Significant improvement in throughput results by the use of this electron beam method and apparatus which preferably employs magnetic deflection for the sequential scanning the subfields and electric deflection for vector scanning within the subfield.
摘要翻译：一种电子束方法和装置，用于写入诸如半导体晶片的图案，其中写入场被划分成具有预定周期的大量重叠子场。子场到子场移动是以阶梯式顺序扫描（例如光栅）进行的，而子场内的图案使用向量扫描寻址并使用顺序扫描进行写入。通过使用该电子束方法和优选采用磁偏转进行顺序扫描子场的装置和在子场内的矢量扫描的电偏转的装置，可以显着提高吞吐量。

2. 发明授权

US6167524A Apparatus and method for efficient battery utilization in portable personal computers 失效
标题翻译：便携式个人计算机中有效利用电池的装置和方法
公开(公告)号：US6167524A
公开(公告)日：2000-12-26
申请号：US56300
申请日：1998-04-06
申请人： Kenneth J. Goodnow , Michel S. Michail , Janak G. Patel , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Janak G. Patel , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： G06F1/32 , G06F9/38 , G06F1/26 , G06F1/28 , G06F1/30
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/3287 , G06F9/3836 , G06F9/3842 , G06F9/3869 , Y02D10/171
摘要： An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.
摘要翻译：一种通过动态分配系统逻辑电力来控制便携式个人计算机中的功耗的装置和方法。计算总功耗，并将其与最佳功率效率值进行比较。每个执行单元的预期功耗值以实际或压缩形式存储在查找表中。如果预期的总功耗值超过功率效率值，则使所选择的执行单元无效。相反，如果功率效率值超过预期的总功耗值，则添加执行单元功能以便保持对电池的电平电流需求。

3. 发明授权

US5091659A Composite logic gate circuit with means to reduce voltage required by logic transistors from external source 失效
标题翻译：复合逻辑门电路具有降低逻辑晶体管从外部源所需电压的方法
公开(公告)号：US5091659A
公开(公告)日：1992-02-25
申请号：US685859
申请日：1991-04-16
申请人： Michel S. Michail , James R. Struk
发明人： Michel S. Michail , James R. Struk
IPC分类号： H03K19/00 , H03K19/086
CPC分类号： H03K19/001 , H03K19/086
摘要： A logic circuit has a plurality of serially connected logic units wherein each unit is a gate comprising a resistor serially connected to a combination of a plurality of transistors connected together in parallel. The transistors of the logic circuit are arranged to enable reduction of the requisite voltage to be provided by an external power source. By reduction of the voltage, the values of resistance can be reduced without exceeding a power dissipation budget. Alternate logic units, in a series of logic units, are constructed of PNP and NPN transistors. Furthermore, the voltage drop across a transistor of a preceding logic unit, as measured between the emitter and collector terminals of a transistor, is applied, essentially, across the base-emitter junction of a transistor in a succeeding logic unit so as to provide a supply of base current to the transistor of the succeeding logic unit without danger of saturating the transistor and without cutting off current flow to the transistor. Furthermore, the magnitude of resistance of the resistor of the preceding logic unit is sufficient to limit base current to the transistor of the succeeding logic unit so as to avoid saturation of the transistor in the succeeding logic unit. An output signal of the logic unit may be applied to an inverter circuit, and speed-up capacitors may be applied in emitter circuits of the inverter and the preceding logic unit for a sharpening of both leading and trailing edges of a logic signal.
摘要翻译：逻辑电路具有多个串联的逻辑单元，其中每个单元是包括串联连接到并联连接在一起的多个晶体管的组合的电阻器的栅极。逻辑电路的晶体管被布置成能够减少由外部电源提供的必需电压。通过降低电压，可以在不超过功率耗散预算的情况下降低电阻值。一系列逻辑单元中的备用逻辑单元由PNP和NPN晶体管构成。此外，在晶体管的发射极和集电极端子之间测量的先前逻辑单元的晶体管上的电压降，基本上跨越后续逻辑单元中的晶体管的基极 - 发射极结，以提供向后续逻辑单元的晶体管提供基极电流，而不会使晶体管饱和而不会切断到晶体管的电流。此外，前一逻辑单元的电阻器的电阻的大小足以将基极电流限制到后续逻辑单元的晶体管，以避免后续逻辑单元中的晶体管的饱和。可以将逻辑单元的输出信号施加到逆变器电路，并且可以将加速电容器施加在反相器和前一逻辑单元的发射极电路中，以用于锐化逻辑信号的前沿和后沿。

4. 发明授权

US4991138A High speed memory cell with multiple port capability 失效
标题翻译：具有多端口功能的高速存储单元
公开(公告)号：US4991138A
公开(公告)日：1991-02-05
申请号：US331989
申请日：1989-04-03
申请人： Joseph R. Cavaliere , Alan K. Chan , Michel S. Michail
发明人： Joseph R. Cavaliere , Alan K. Chan , Michel S. Michail
IPC分类号： G11C8/16 , G11C11/411
CPC分类号： G11C11/4113 , G11C8/16
摘要： A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; a sensing circuit connected to each of the base-collector terminals in the transistor pair, each of the sensing circuits including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connected to the word line, and (c) a circuit connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; a writing circuit connected to each of the transistors in the transistor pair, the writing circuit including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and a circuit for supplying constant current to each of the base-collector terminals and to each of the commonly connected anodes of the first and second diodes. The memory cell permits read access or select while maintaining the voltages on the latch nodes stable.

5. 发明授权

US5902044A Integrated hot spot detector for design, analysis, and control 失效
标题翻译：集成热点检测器，用于设计，分析和控制
公开(公告)号：US5902044A
公开(公告)日：1999-05-11
申请号：US883911
申请日：1997-06-27
申请人： Wilbur Pricer , Kenneth Joseph Goodnow , Michel S. Michail , Janak Ghanshyambhai Patel , Sebastian T. Ventrone
发明人： Wilbur Pricer , Kenneth Joseph Goodnow , Michel S. Michail , Janak Ghanshyambhai Patel , Sebastian T. Ventrone
IPC分类号： G01K3/14 , G01K7/00
CPC分类号： G01K3/14
摘要： A matrix of thermal sensors is provided for accurately evaluating the thermal characteristics of an integrated circuit. The integrated circuit is evenly divided into a plurality of sectors in which a thermal comparison to a known thermal mass will be performed. Each sector includes at least one dual cell comprising a local thermal sensor for providing an output corresponding to a local temperature of the integrated circuit in that sector, and a background thermal sensor. The outputs of selective ones of the background thermal sensors are combined to provide a signal corresponding to a background temperature of the integrated circuit. A decoder/enabler arrangement is used to selectively gate the output of a specific local thermal sensor in a sector to a difference circuit where it is compared to the collective output of selected ones of the background sensors to generate a thermal measurement of the sector under test.
摘要翻译：提供了一种热传感器矩阵，用于精确评估集成电路的热特性。集成电路被均匀地分成多个扇区，其中将对已知的热质量进行热比较。每个扇区包括至少一个双电池，其包括本地热传感器，用于提供对应于该扇区中的集成电路的局部温度的输出和背景热传感器。背景热传感器中的选择性传感器的输出被组合以提供对应于集成电路的背景温度的信号。解码器/使能器布置用于选择性地将扇区中的特定局部热传感器的输出门控到差分电路，其中与所选择的背景传感器的集合输出进行比较以产生被测扇区的热测量。

6. 发明授权

US4806785A Half current switch with feedback 失效
标题翻译：具有反馈的半电流开关
公开(公告)号：US4806785A
公开(公告)日：1989-02-21
申请号：US156761
申请日：1988-02-17
申请人： Michel S. Michail , James L. Walsh
发明人： Michel S. Michail , James L. Walsh
IPC分类号： H03K19/00 , H03K19/082 , H03K19/086 , H03K19/08
CPC分类号： H03K19/001 , H03K19/082 , H03K19/086 , Y10T307/865
摘要： A half current switch comprising: at least one input transistor, a load resistance connected between a first voltage reference and the collector of the input transistor, a constant-current resistance connected between the emitter of the input transistor and a second voltage reference, and a feedback means including at least one feedback connected to the constant-current resistance. The feedback means further includes means for biasing the feedback transistor to drive a current through the constant current resistance which, when flowing, increases with an increasing main current and decreases with a decreasing main current through the input transistor. The feedback means thus causes a constant current to be drawn by the input transistor when it is conducting, thereby controlling the capacitance of the input transistor while maintaining the output level constant.In a preferred embodiment, the feedback means comprises a PNP transistor with its base connected to the collector of the input transistor, with its emitter connected to the first voltage reference, and with its collector connected to the emitter of the input transistor. The PNP transistor not only acts as a feedback device to control current, but also acts to prevent oscillations when a speed-up capacitor is used in the circuit.

7. 发明授权

US06658634B1 Logic power optimization algorithm 失效
标题翻译：逻辑功率优化算法
公开(公告)号：US06658634B1
公开(公告)日：2003-12-02
申请号：US09073999
申请日：1998-05-07
申请人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.
摘要翻译：公开了一种用于消除在逻辑网络中不必要的逻辑切换的系统和方法。该方法和系统可以直接并入逻辑综合软件中，或者可以手动实现。提供了用于识别关键网络，然后在关键网络处插入网络锁存器的机制，其中每个网络锁存器由也控制相关输出锁存器的使能信号控制。每个网络锁存器包括一个电路，该电路可以在命令上保持给定逻辑节点上的最后一个逻辑电平。

8. 发明授权

US6034568A Broadband dc amplifier technique with very low offset voltage 失效
标题翻译：宽带直流放大器技术具有非常低的失调电压
公开(公告)号：US6034568A
公开(公告)日：2000-03-07
申请号：US97484
申请日：1998-06-15
申请人： Anthony R. Bonaccio , Michel S. Michail , W. David Pricer
发明人： Anthony R. Bonaccio , Michel S. Michail , W. David Pricer
IPC分类号： H03F1/48 , H03F3/45
CPC分类号： H03F1/483
摘要： An operational amplifier with two differential input stages is used to separately achieve low offset voltage and broad bandwidth characteristics. One input stage addresses dc and low frequency signals while the other addresses broadband frequencies. All transistors forming the dc stage are biased in the sub-threshold region. Following the two differential input stages, the signal paths are recombined in a capacitive cross-over network that provides outputs for subsequent amplification. The cross over frequency is adjustable from 15 kHz to 50 kHz using small practical values for the cross-over capacitor. The gain balance between the two input stages is adjustable by resistors and/or predetermined width/length ratios of the operational amplifier transistors.
摘要翻译：具有两个差分输入级的运算放大器用于分别实现低失调电压和宽带宽特性。一个输入级用于解决直流和低频信号，而其他输入级则处理宽带频率。形成直流级的所有晶体管都被偏置在子阈值区域中。在两个差分输入级之后，信号路径在电容交叉网络中重新组合，提供用于后续放大的输出。交叉频率的交叉电容可以使用小的实际值从15 kHz到50 kHz进行交叉。两个输入级之间的增益平衡可通过运算放大器晶体管的电阻和/或预定的宽度/长度比来调节。

9. 发明授权

US4137459A Method and apparatus for applying focus correction in E-beam system 失效
标题翻译：在电子束系统中应用聚焦校正的方法和装置
公开(公告)号：US4137459A
公开(公告)日：1979-01-30
申请号：US877198
申请日：1978-02-13
申请人： Drew E. Albrecht , Samuel K. Doran , Michel S. Michail , Hannon S. Yourke
发明人： Drew E. Albrecht , Samuel K. Doran , Michel S. Michail , Hannon S. Yourke
IPC分类号： H01L21/027 , H01J37/21 , H01J37/304 , A61K27/02
CPC分类号： H01J37/304 , H01J37/21
摘要： A method and apparatus for applying focus correction to an E-beam or charged particle system to compensate for wafer warp and mask tilt. In an electron beam system including a registration system which measures the position of four registration marks with the beam and calculates the apparent magnification error of a given chip, means are also provided for using magnification and rotation error information to calculate a height error factor and to apply a compensating current to a dynamic focusing coil of the electron beam to move the effective beam focal plane to a position which matches the wafer or mask plane at each chip site.
摘要翻译：将聚焦校正应用于电子束或带电粒子系统以补偿晶片翘曲和掩模倾斜的方法和装置。在包括测量四个对准标记与光束的位置并计算给定芯片的视在放大误差的配准系统的电子束系统中，还提供了使用放大率和旋转误差信息来计算高度误差因子的装置，并且将补偿电流施加到电子束的动态聚焦线圈，以将有效束焦平面移动到与每个芯片位置处的晶片或掩模平面匹配的位置。

10. 发明授权

US06452448B1 Family of analog amplifier and comparator circuits with body voltage control 有权
标题翻译：具有体电压控制的模拟放大器和比较器电路系列
公开(公告)号：US06452448B1
公开(公告)日：2002-09-17
申请号：US09616550
申请日：2000-07-14
申请人： Anthony R. Bonaccio , Michel S. Michail , Wilbur D. Pricer , Steven J. Tanghe
发明人： Anthony R. Bonaccio , Michel S. Michail , Wilbur D. Pricer , Steven J. Tanghe
IPC分类号： H03F345
CPC分类号： H03F3/45748 , H03F3/4521 , H03F2203/45342 , H03F2203/45658 , H03F2203/45711
摘要： A structure for an amplifier circuit which includes a pair of source-coupled differential transistors, each of source-coupled differential transistors having a body and a gate, and input transistors electrically connected to the source-coupled transistors. Also, the input transistors load the body and the gate of the source-coupled transistors with positive feedback signals. As a result, a differential gain is increased and a common mode gain is not increased. The output of the pair of source-coupled differential transistors is directed to second pair of transistors. The second pair of transistors generates mirrored voltages which track with input voltages. The second pair of transistors generates mirrored voltages translated by an offset voltage to values near ground, mirrored voltages which represent a voltage gain over an input voltage, and mirrored voltages which are largely differential and includes approximately no common mode input voltage.
摘要翻译：一种用于放大器电路的结构，其包括一对源极耦合差分晶体管，每个源极耦合差分晶体管具有主体和栅极，以及输入晶体管，电连接到源耦合晶体管。此外，输入晶体管负载负极反馈信号的源极耦合晶体管的主体和栅极。结果，差分增益增加并且共模增益不增加。一对源极耦合差分晶体管的输出被引导到第二对晶体管。第二对晶体管产生用输入电压跟踪的镜像电压。第二对晶体管产生由偏移电压转换为接近接近的值的镜像电压，表示输入电压上的电压增益的镜像电压和大幅度差分的近似不包含共模输入电压的镜像电压。

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