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1. 发明授权

US5960294A Method of fabricating a semiconductor device utilizing polysilicon grains 失效
标题翻译：制造利用多晶硅晶粒的半导体器件的方法
公开(公告)号：US5960294A
公开(公告)日：1999-09-28
申请号：US6126
申请日：1998-01-13
申请人： John K. Zahurak , Scott J. DeBoer , Randhir P.S. Thakur , Mark Fischer
发明人： John K. Zahurak , Scott J. DeBoer , Randhir P.S. Thakur , Mark Fischer
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/84 , H01L28/91
摘要： A method of fabricating capacitors for a dynamic random access memory device reduces double bit failures or shorts in the device. The method includes providing a semiconductor substrate underlying an insulative layer having a plurality of storage cells formed therein electrically connected to the substrate. A first conductive layer of rugged polysilicon, which functions as a first capacitor plate, is formed over the insulative layer in an oxygen-free atmosphere such that the first conductive layer is without natural oxides on the surface thereof. The surface of the first conductive layer in the oxygen-free atmosphere is then conditioned by a rapid thermal nitridization process which forms a silicon nitride film thereon. Thereafter, portions of the first conductive layer are removed from the insulative layer such that the plurality of storage cells are electrically isolated from one another. A dielectric layer is then formed over the first conductive layer and exposed insulative layer, followed by a second conductive layer, functioning as a second capacitor plate, being formed over the dielectric layer to complete the capacitor structure.
摘要翻译：一种制造用于动态随机存取存储器件的电容器的方法减少了器件中的双位故障或短路。该方法包括在其上形成有电连接到基板的多个存储单元的绝缘层下方提供半导体基板。在无氧气氛中的绝缘层上形成用作第一电容器板的凹凸多晶硅的第一导电层，使得第一导电层在其表面上不具有天然氧化物。然后在无氧气氛中的第一导电层的表面通过在其上形成氮化硅膜的快速热氮化工艺进行调理。此后，将第一导电层的部分从绝缘层移除，使得多个存储单元彼此电隔离。然后在第一导电层和暴露的绝缘层上形成电介质层，然后在电介质层上形成用作第二电容器板的第二导电层，以完成电容器结构。

2. 发明授权

US07119397B2 Double blanket ion implant method and structure 有权
标题翻译：双层离子注入法和结构
公开(公告)号：US07119397B2
公开(公告)日：2006-10-10
申请号：US10768081
申请日：2004-02-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

3. 发明授权

US06372601B1 Isolation region forming methods 失效
公开(公告)号：US06372601B1
公开(公告)日：2002-04-16
申请号：US09146838
申请日：1998-09-03
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L21762
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

4. 发明授权

US06967146B2 Isolation region forming methods 失效
标题翻译：隔离区形成方法
公开(公告)号：US06967146B2
公开(公告)日：2005-11-22
申请号：US10799794
申请日：2004-03-11
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L21/302 , H01L21/033 , H01L21/3065 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

5. 发明授权

US06593206B2 Isolation region forming methods 失效
公开(公告)号：US06593206B2
公开(公告)日：2003-07-15
申请号：US10076684
申请日：2002-02-14
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

6. 发明授权

US06309973B1 Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
标题翻译：形成导电投影的半导体处理方法和增加对准公差的方法
公开(公告)号：US06309973B1
公开(公告)日：2001-10-30
申请号：US09507193
申请日：2000-02-18
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21302
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a, portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.
摘要翻译：描述形成导电突起的半导体加工方法和增加对准公差的方法。在一个实施方案中，导电突起形成在衬底表面区域上，并且包括与其连接的上表面和侧表面以限定拐角区域。导电突起的角区域随后被倒角以增加相对于其的对准公差。在另一实施方案中，导电插塞形成在一对导线之间的衬底节点位置之上并且具有最上表面。导电插塞的材料被不均匀地移除以限定第二最上表面，其中至少一部分的表面布置在高于导电线的高度上。在一个方面，可以通过刻蚀导电插塞去除导电插塞材料。在另一方面，导电插塞材料用掺杂剂不均匀掺杂，并且以比含有较低浓度掺杂剂的插塞材料更大的速率蚀刻含有较大浓度掺杂剂的导电插塞材料。

7. 发明授权

US6083803A Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
公开(公告)号：US6083803A
公开(公告)日：2000-07-04
申请号：US32254
申请日：1998-02-27
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21/302 , G03F7/075 , G03F7/16 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.

8. 发明授权

US06710420B2 Semiconductor construction of a trench 有权
标题翻译：半导体构造的沟槽
公开(公告)号：US06710420B2
公开(公告)日：2004-03-23
申请号：US10241923
申请日：2002-09-11
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

9. 发明授权

US06482707B1 Method of improving static refresh 有权
标题翻译：改善静态刷新的方法
公开(公告)号：US06482707B1
公开(公告)日：2002-11-19
申请号：US09532094
申请日：2000-03-21
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

10. 发明授权

US06410951B1 Structure for improving static refresh 有权
公开(公告)号：US06410951B1
公开(公告)日：2002-06-25
申请号：US09822249
申请日：2001-04-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

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