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1. 发明授权

US07124245B1 Data storage system having cache memory manager with packet switching network 有权
公开(公告)号：US07124245B1
公开(公告)日：2006-10-17
申请号：US10675039
申请日：2003-09-30
申请人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
发明人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
IPC分类号： G06F12/00
CPC分类号： G06F12/0866
摘要： A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.

2. 发明授权

US07437425B2 Data storage system having shared resource 有权
标题翻译：数据存储系统具有共享资源
公开(公告)号：US07437425B2
公开(公告)日：2008-10-14
申请号：US10675040
申请日：2003-09-30
申请人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
发明人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
IPC分类号： G06F15/167
CPC分类号： H04L67/1097 , G06F11/1666 , H04L49/101 , H04L49/3009 , H04L69/40
摘要： A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.
摘要翻译：一种具有多个导向器的系统接口，所述导向器的一部分适于耦合到主计算机/服务器，并且所述导向器的另一部分适于耦合到一组磁盘驱动器。多个导向器通过网络相互连接。提供了共享资源部分，其具有在多个董事之间共享的资源。公共共享资源部分包括由多个董事使用的共享计算机代码。代码包括用于引导多个导向器中的每一个的计算机代码。公共共享代码存储部分通过网络与董事互连。提供了第二个冗余公共共享资源部分。网络是分组交换网络。

3. 发明授权

US07454536B1 Data system having a virtual queue 有权
标题翻译：数据系统具有虚拟队列
公开(公告)号：US07454536B1
公开(公告)日：2008-11-18
申请号：US10675166
申请日：2003-09-30
申请人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
发明人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
IPC分类号： G06F3/00
CPC分类号： G06F13/387
摘要： A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.
摘要翻译：一种排队系统，其中至少一个具有出站队列的输入/输出（I / O）接口。多个处理单元耦合到至少一个I / O接口。每个处理单元耦合到对应的处理单元存储器。每个处理单元存储器具有用于这种耦合处理单元的入站队列。所述至少一个I / O接口出站队列在由一个处理单元处理之后存储返回到I / O接口的出站信息。 I / O接口创建用于存储在处理器单元存储器的入站队列中的队列索引。 I / O接口包括转换表，该表存储在多个处理单元的生产者索引的位置以及用于这些多个处理单元的消费者索引。

4. 发明授权

US07272668B1 System having backplane performance capability selection logic 有权
标题翻译：具有背板性能能力选择逻辑的系统
公开(公告)号：US07272668B1
公开(公告)日：2007-09-18
申请号：US10606872
申请日：2003-06-26
申请人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
发明人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
IPC分类号： G06F3/00 , G06F13/00 , G06F13/42 , G06F11/00
CPC分类号： G06F1/181 , G06F1/184 , G06F1/185 , G06F1/186 , G06F3/0601 , G06F2003/0692
摘要： A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.
摘要翻译：具有多个印刷电路的系统具有在其上具有电气部件的每个印刷电路。背板携带指示插入到该背板中的多个印刷电路板上的电气部件的性能特征的信号。性能特征可以是例如组件速度，操作协议等。在检测到这种不兼容性时，系统启动被中断。在启动之后，当插入其上具有电气部件的附加印刷电路，其操作与多个印刷电路板上的电气部件不兼容的操作进入背板时，这种附加印刷电路上的电气部件将不会电耦合到电子部件在多个印刷电路板的电气部件上的附加印刷电路板上。

5. 发明授权

US07552282B1 Method, computer readable medium, and data storage system for selective data replication of cached data 有权
标题翻译：方法，计算机可读介质和数据存储系统，用于缓存数据的选择性数据复制
公开(公告)号：US07552282B1
公开(公告)日：2009-06-23
申请号：US10911365
申请日：2004-08-04
申请人： Michael Bermingham , Kendell A. Chilton , Robert DeCrescenzo , Mark J. Halstead , Haim Kopylovitz , Steven T. McClure , James M. McGillis , Ofer E. Michael , Brett D. Niver , John K. Walton
发明人： Michael Bermingham , Kendell A. Chilton , Robert DeCrescenzo , Mark J. Halstead , Haim Kopylovitz , Steven T. McClure , James M. McGillis , Ofer E. Michael , Brett D. Niver , John K. Walton
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/387 , G06F12/0802
摘要： Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.
摘要翻译：描述了选择性数据复制的技术。如果缓存数据被表征为关键，则会被复制。关键数据可能包括与写入I / O操作相关联的数据。为复制数据选择缓存位置，使得第一位置被映射到第一存储器板，并且第二位置被映射到第二存储器板。读操作的数据不会在缓存中复制。其他非缓存数据是关键的，因此被复制包括元数据。从同一缓存位置池进行I / O操作时动态地选择读写I / O操作数据的缓存位置。

6. 发明授权

US07020754B1 Method and system for maintaining data integrity using dual write operations 有权
标题翻译：使用双重写入操作来维护数据完整性的方法和系统
公开(公告)号：US07020754B1
公开(公告)日：2006-03-28
申请号：US10022080
申请日：2001-12-13
申请人： John K. Walton , Kendell A. Chilton
发明人： John K. Walton , Kendell A. Chilton
IPC分类号： G06F12/00
CPC分类号： G06F11/2087 , G06F12/0866
摘要： In one embodiment, a data storage system is provided may include an input/output (I/O) controller, and first and second memory boards. The controller may receive data and a request to store the data in the system, and may include memory for initially storing the data. The first memory board may store, in response to a first memory storage request, a first copy of the data initially stored in the controller. The first memory board may provide to the controller a first status indication indicating whether the first memory board successfully stored the first copy. The second memory board may store, in response to receipt of a second memory storage request, a second copy of the data. The controller may provide a second status indication, indicating whether the request to store the data in the system was successful.
摘要翻译：在一个实施例中，提供的数据存储系统可以包括输入/输出（I / O）控制器以及第一和第二存储器板。控制器可以接收数据和将数据存储在系统中的请求，并且可以包括用于初始存储数据的存储器。第一存储器板可以响应于第一存储器存储请求存储最初存储在控制器中的数据的第一副本。第一存储器板可以向控制器提供指示第一存储器板是否成功存储第一副本的第一状态指示。第二存储器板可以响应于接收到第二存储器存储请求而存储数据的第二副本。控制器可以提供第二状态指示，指示在系统中存储数据的请求是否成功。

7. 发明授权

US06910145B2 Data transmission across asynchronous clock domains 有权
标题翻译：跨异步时钟域的数据传输
公开(公告)号：US06910145B2
公开(公告)日：2005-06-21
申请号：US10021949
申请日：2001-12-13
申请人： Christopher S. MacLellan , Gregory S. Robidoux , John K. Walton , Kendell A. Chilton
发明人： Christopher S. MacLellan , Gregory S. Robidoux , John K. Walton , Kendell A. Chilton
IPC分类号： G06F3/06 , G06F12/00 , G06F13/00 , H04L7/02
CPC分类号： G06F3/061 , G06F3/0656 , G06F3/067 , H04L7/005 , H04L7/02
摘要： In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.
摘要翻译：在本发明的一个实施例中，提供了一种用于将数据和相关控制信息从第一时钟域传送到第二时钟域的系统。该系统可以包括第一逻辑部分，该第一逻辑部分可以生成相应的识别信息，所述识别信息可用于识别由相应数据和相关控制信息表示的相应信息类型。系统还可以包括可以以第一时钟域中使用的第一时钟速率接收和存储相应数据和相关控制信息的存储器。存储器还可以与各个数据和相关控制信息相关联地存储相应的标识信息。存储器可以被配置为允许在第二时钟域中使用的第二时钟速率检索相应数据，相应的相关控制信息以及存储在存储器中的相应标识信息。

8. 发明授权

US06877061B2 Data storage system having dummy printed circuit boards 有权
标题翻译：具有虚拟印刷电路板的数据存储系统
公开(公告)号：US06877061B2
公开(公告)日：2005-04-05
申请号：US10112598
申请日：2002-03-28
申请人： Robert A. Thibault , Daniel Castel , Brian Gallagher , Paul C. Wilson , John K. Walton , Christopher S. MacLellan
发明人： Robert A. Thibault , Daniel Castel , Brian Gallagher , Paul C. Wilson , John K. Walton , Christopher S. MacLellan
IPC分类号： G06F13/00 , G06F13/14 , H05K7/10
CPC分类号： H05K7/1459 , G06F2213/0038
摘要： A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers. The method includes wiring the backplane to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the global memory to the first plurality of directors and to the second plurality of director. The method and system allows the same wired backplane to be used with systems having a different number of memory and director boards and still enable dual-write and redundancy to the global memory.
摘要翻译：一种用于产生数据存储系统的方法和系统，用于通过系统接口在主计算机/服务器和一组磁盘驱动器之间传送数据。系统接口具有多个第一导向器，多个第二导向器和全局存储器。该方法包括：提供具有适于在其中插入多个印刷电路板的槽的背板。印刷电路板包括：多个具有第一导体的第一导向板; 具有第二导体的多个第二印刷电路板; 提供全局存储器的多个存储器印刷电路板; 多个具有第一跳线的虚拟第一导向板; 多个具有第二跳线的虚拟第二导向板; 具有第三跳线的多个虚拟存储器板。该方法包括布线背板以实现第一，第二和第三跳线之间的连接，以将第一多个导向器与主计算机/服务器互连，将多个第二多个导向器连接到磁盘驱动器组，并将全局存储器第一批董事和第二名董事。该方法和系统允许与具有不同数量的存储器和引导器板的系统一起使用相同的有线背板，并且仍然允许对全局存储器进行双重写入和冗余。

9. 发明授权

US06904556B2 Systems and methods which utilize parity sets 有权
标题翻译：利用奇偶校验集的系统和方法
公开(公告)号：US06904556B2
公开(公告)日：2005-06-07
申请号：US09927042
申请日：2001-08-09
申请人： John K. Walton , Michael Bermingham , Christopher S. MacLellan
发明人： John K. Walton , Michael Bermingham , Christopher S. MacLellan
IPC分类号： G06F12/08 , G06F3/06 , G06F11/10 , G06F12/16 , G11C29/00
CPC分类号： G06F11/108 , G06F2211/1009
摘要： A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.
摘要翻译：提供了一种存储系统及其使用方法。该系统的一个实施例包括被配置为包括多个存储器段的半导体存储器。内存段被分组成组。每个组包括N个相应的存储器段，其中N是整数。在每个相应的存储器段组中，N个相应的存储器段包括相应的数据段和相应的奇偶校验段。同样在各组存储器段中，相应组中的相应奇偶校验段存储可以通过存储在相应组中的相应数据段中的逻辑异或相应数据值来计算的相应数据值P.

10. 发明授权

US6138195A Method and apparatus for hot-plugging circuit boards having low voltage logic parts into a higher voltage backplane 失效
标题翻译：将具有低电压逻辑部件的电路板热插入更高电压背板的方法和装置
公开(公告)号：US6138195A
公开(公告)日：2000-10-24
申请号：US45037
申请日：1998-03-20
申请人： Michael Bermingham , Christopher S. MacLellan , John K. Walton
发明人： Michael Bermingham , Christopher S. MacLellan , John K. Walton
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081 , G06F13/4068
摘要： A method and apparatus for hot-plugging circuit boards having lower voltage logic devices into a higher voltage backplane in a manner that minimizes overvoltage stress during system power-up, or during a lower voltage power failure. The method and apparatus ensures that the lower voltage device(s') power input reaches at least a nominal input level before any other inputs of the device are driven to a level greater than or equal to an expected input level. Dedicated output pins on lower voltage logic device(s) are configured to issue a control output signal for enabling higher voltage devices. Output enable terminals for the higher voltage parts, which are connected to respective control outputs from a lower voltage device, are normally in a disabled state as a function of pull-up or pull-down circuitry. A respective control output signal is provided for each higher voltage device output enable to enable the outputs of the higher voltage device when the voltage supply input to the lower voltage device is at substantially full voltage.
摘要翻译：一种用于将具有较低电压逻辑器件的电路板热插入到较高电压背板中的方法和装置，其方法是以最小化系统上电期间过电压应力或在较低电压电源故障期间的方式。该方法和装置确保在装置的任何其它输入被驱动到大于或等于预期输入电平的电平之前，低电压装置（s'）功率输入达到至少一个标称输入电平。低电压逻辑器件上的专用输出引脚被配置为发出控制输出信号，以使更高电压的器件成为可能。与较低电压设备连接到相应控制输出的较高电压部分的输出使能端子通常作为上拉或下拉电路的功能处于禁止状态。为每个较高电压器件输出使能提供相应的控制输出信号，以便当输入到较低电压器件的电压电源处于基本满电压时，能够使得较高电压器件的输出。

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