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1. 发明授权

US06877061B2 Data storage system having dummy printed circuit boards 有权
标题翻译：具有虚拟印刷电路板的数据存储系统
公开(公告)号：US06877061B2
公开(公告)日：2005-04-05
申请号：US10112598
申请日：2002-03-28
申请人： Robert A. Thibault , Daniel Castel , Brian Gallagher , Paul C. Wilson , John K. Walton , Christopher S. MacLellan
发明人： Robert A. Thibault , Daniel Castel , Brian Gallagher , Paul C. Wilson , John K. Walton , Christopher S. MacLellan
IPC分类号： G06F13/00 , G06F13/14 , H05K7/10
CPC分类号： H05K7/1459 , G06F2213/0038
摘要： A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers. The method includes wiring the backplane to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the global memory to the first plurality of directors and to the second plurality of director. The method and system allows the same wired backplane to be used with systems having a different number of memory and director boards and still enable dual-write and redundancy to the global memory.
摘要翻译：一种用于产生数据存储系统的方法和系统，用于通过系统接口在主计算机/服务器和一组磁盘驱动器之间传送数据。系统接口具有多个第一导向器，多个第二导向器和全局存储器。该方法包括：提供具有适于在其中插入多个印刷电路板的槽的背板。印刷电路板包括：多个具有第一导体的第一导向板; 具有第二导体的多个第二印刷电路板; 提供全局存储器的多个存储器印刷电路板; 多个具有第一跳线的虚拟第一导向板; 多个具有第二跳线的虚拟第二导向板; 具有第三跳线的多个虚拟存储器板。该方法包括布线背板以实现第一，第二和第三跳线之间的连接，以将第一多个导向器与主计算机/服务器互连，将多个第二多个导向器连接到磁盘驱动器组，并将全局存储器第一批董事和第二名董事。该方法和系统允许与具有不同数量的存储器和引导器板的系统一起使用相同的有线背板，并且仍然允许对全局存储器进行双重写入和冗余。

2. 发明授权

US07007194B1 Data storage system having point-to-point configuration 有权
标题翻译：具有点到点配置的数据存储系统
公开(公告)号：US07007194B1
公开(公告)日：2006-02-28
申请号：US09606730
申请日：2000-06-29
申请人： Paul C. Wilson , Mark Zani , Farouk Khan , Christopher S. MacLellan , John K. Walton , Steven MacArthur , Kendall A. Chilton , William Tuccio , Robert A. Thibault
发明人： Paul C. Wilson , Mark Zani , Farouk Khan , Christopher S. MacLellan , John K. Walton , Steven MacArthur , Kendall A. Chilton , William Tuccio , Robert A. Thibault
IPC分类号： G06F11/00
CPC分类号： G06F11/2089 , G06F11/201 , G06F12/0866 , G06F2201/85
摘要： A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.
摘要翻译：系统接口包括多个第一导向器，多个第二导向器，数据传输部分和消息网络。数据传送部分包括高速缓冲存储器。高速缓存存储器耦合到多个第一和第二导向器。消息传递网络独立于数据传送部分运行，并且这样的网络耦合到多个第一董事和多个第二董事。第一和第二位董事通过消息传递网络响应第一任董事和第二任董事之间的信息，控制第一任董事与第二任董事之间的数据转移，以促进第一任董事与第二任董事之间的数据转移。数据通过数据传输部分的高速缓冲存储器。一种用于操作适于在主计算机/服务器和一组磁盘驱动器之间传送数据的数据存储系统的方法。该方法包括通过消息传递网络传送消息，数据通过高速缓冲存储器在主机计算机/服务器和磁盘驱动器组之间传输，这样的消息网络独立于高速缓冲存储器。

3. 发明授权

US07102893B1 Methods and apparatus for forming a cohesive backplane interconnect system 有权
标题翻译：用于形成内聚背板互连系统的方法和装置
公开(公告)号：US07102893B1
公开(公告)日：2006-09-05
申请号：US10673829
申请日：2003-09-29
申请人： Stephen D. MacArthur , Rudy Bauer , William Frederick Baxter, III , Paul C. Wilson
发明人： Stephen D. MacArthur , Rudy Bauer , William Frederick Baxter, III , Paul C. Wilson
IPC分类号： H01R12/16
CPC分类号： G02B6/4452
摘要： An assembly couples first and second backplanes together. The first backplane is configured to carry first electrical backplane signals among a first set of circuit boards. The second backplane is configured to carry second electrical backplane signals among a second set of circuit boards. The assembly includes a first switch configured to convey at least some of the first electrical backplane signals between circuit boards of the first set of circuit boards. The assembly further includes a second switch configured to convey at least some of the second electrical backplane signals between circuit boards of the second set of circuit boards. The assembly further includes a fiber optic cable joining the first and second switches together. The first and second switches are configured to exchange fiber optic signals through the fiber optic cable thus forming a cohesive backplane interconnect system between the first and second sets of circuit boards.
摘要翻译：组件将第一和第二背板耦合在一起。第一背板被配置为在第一组电路板之间承载第一电背板信号。第二背板被配置为在第二组电路板之间承载第二电背板信号。组件包括第一开关，其被配置为在第一组电路板的电路板之间传送第一电背板信号中的至少一些。组件还包括第二开关，其被配置为在第二组电路板的电路板之间传送第二电背板信号中的至少一些。组件还包括将第一和第二开关连接在一起的光纤电缆。第一和第二开关被配置为通过光纤电缆交换光纤信号，从而在第一和第二组电路板之间形成一个内聚的背板互连系统。

4. 发明授权

US07143306B2 Data storage system 有权
标题翻译：数据存储系统
公开(公告)号：US07143306B2
公开(公告)日：2006-11-28
申请号：US10403262
申请日：2003-03-31
申请人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno , Paul C. Wilson
发明人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno , Paul C. Wilson
IPC分类号： G06F11/00
CPC分类号： G06F12/084 , G06F11/2053 , G06F12/0868 , G06F2212/261
摘要： A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.
摘要翻译：一种具有高速缓冲存储器和多个导向器的系统接口。多个董事中的每一个都包括耦合在这样一个董事的输入之间的数据管。数据管道包括数据管道存储器和用于控制数据管道存储器的数据管道存储器控制器。每个导体包括耦合到数据管存储器控制器的微处理器。该系统包括耦合到高速缓存存储器以在存储器之间传送数据的切换网络：（a）通过数据管道存储器输入多个导向器中的所选择的一个; （b）所述微处理器和所述数据管道存储器，通过所述多个董事中选定的一个的所述数据管道存储器控制器; 以及（c）所述微处理器和所述数据管存储器控制器，同时绕过所述多个导向器中所选择的一个的所述数据管道存储器。

5. 发明授权

US5544330A Fault tolerant interconnect topology using multiple rings 失效
标题翻译：使用多个环的容错互连拓扑
公开(公告)号：US5544330A
公开(公告)日：1996-08-06
申请号：US275005
申请日：1994-07-13
申请人： David S. Bither , Charles S. F. Loewy , Paul C. Wilson
发明人： David S. Bither , Charles S. F. Loewy , Paul C. Wilson
IPC分类号： G06F11/00 , G06F11/20 , G06F13/00
CPC分类号： G06F11/2007
摘要： An interconnect topology providing enhanced fault tolerance to a multi-component data processing system. The topology utilizes a plurality of rings for interconnecting multiple system components, or cards, at least two of which are indirectly connected so that communication therebetween is through a third component. Each of the system components is coupled to a set of at least two different rings and includes interface circuits for routing data and a bridge for permitting data to be transferred between the at least two rings.
摘要翻译：互连拓扑，为多组件数据处理系统提供增强的容错能力。该拓扑采用多个环来互连多个系统组件或卡，其中至少两个被间接连接，使得它们之间的通信通过第三组件。每个系统组件耦合到一组至少两个不同的环，并且包括用于路由数据的接口电路和用于允许在至少两个环之间传送数据的桥。

6. 发明授权

US06560573B1 Storage controller with hardware emulation controller for emulation between control processor and transfer circuitry compatible to different processor 有权
标题翻译：具有硬件仿真控制器的存储控制器，可在控制处理器和与不同处理器兼容的传输电路之间进行仿真
公开(公告)号：US06560573B1
公开(公告)日：2003-05-06
申请号：US09365360
申请日：1999-07-30
申请人： Stephen L. Scaringella , Victor W. Tung , Paul C. Wilson , Rudy M. Bauer
发明人： Stephen L. Scaringella , Victor W. Tung , Paul C. Wilson , Rudy M. Bauer
IPC分类号： G06F1312
CPC分类号： G06F9/3879 , G06F11/261
摘要： A hardware emulation controller permits a high performance processor to be used with system circuitry that is configured for operation with a different processor. The hardware emulation controller is capable of modifying signals from the high performance processor for compatibility with the system circuitry. The hardware emulation controller is also capable of modifying signals from the system circuitry for compatibility with the high performance processor.
摘要翻译：硬件仿真控制器允许将高性能处理器与配置为使用不同处理器进行操作的系统电路一起使用。硬件仿真控制器能够修改来自高性能处理器的信号，以与系统电路兼容。硬件仿真控制器还能够修改来自系统电路的信号，以与高性能处理器兼容。

7. 发明授权

US06889301B1 Data storage system 有权
标题翻译：数据存储系统
公开(公告)号：US06889301B1
公开(公告)日：2005-05-03
申请号：US10174115
申请日：2002-06-18
申请人： Paul C. Wilson , Scott Romano , Oren Mano , Robert DeCrescenzo , Steven Kosto , Waiyaki O. Buliro , Matthew Britt Sullivan
发明人： Paul C. Wilson , Scott Romano , Oren Mano , Robert DeCrescenzo , Steven Kosto , Waiyaki O. Buliro , Matthew Britt Sullivan
IPC分类号： G06F11/20 , G06F12/08 , G06F12/00
CPC分类号： G06F11/2007 , G06F11/2005 , G06F11/2089 , G06F11/2094 , G06F12/0866
摘要： A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The interface includes: a global memory; a plurality of front-end directors coupled between the global memory and the host computer/server; and, a plurality of back-end directors coupled between the global memory and the bank of disk drives. Each one of the first directors and each one of the second directors has a data pipe. Each one of such front-end directors passes front-end data between the global memory and the host computer through the data pipe therein and each one of the second directors passing back-end data between the global memory and the bank of disk drives through the data pipe therein. Each one of the first and second directors includes a data pipe controller, responsive to data fed to the data pipe, for performing a selected one of a plurality of functions on the data passing through the data pipe to obtain data from the global memory or to read such data into the global memory. The function is determined by descriptors associated with the data fed to the data pipe therein. A plurality of different, independently operable state machines is provided. Each one of the state machines is adapted to produce control signals for a corresponding one to the functions. A switching section is coupled to the global memory for passing data therethrough between the global memory and the data pipe in accordance with the control signals produced by the state machines.
摘要翻译：一种数据存储系统，用于通过系统接口在主计算机/服务器和一组磁盘驱动器之间传送数据。界面包括：全局内存; 耦合在全局存储器和主计算机/服务器之间的多个前端引导器; 以及耦合在全局存储器和磁盘驱动器组之间的多个后端引导器。第一名董事和第二名董事中的每一位都有一个数据管道。这些前端指导器中的每一个通过其中的数据管道在全局存储器和主计算机之间传递前端数据，并且每个第二控制器通过后端数据在全局存储器和盘驱动器之间通过数据管道。第一和第二导向器中的每一个包括数据管控制器，响应于馈送到数据管道的数据，用于对通过数据管道的数据执行多个功能中的选定一个，以从全局存储器获得数据，或者将这些数据读入全局内存。该功能由与其中提供给数据管道的数据相关联的描述符确定。提供了多个不同的，可独立操作的状态机。状态机中的每一个适于产生用于相应功能的控制信号。切换部分耦合到全局存储器，用于根据由状态机产生的控制信号在全局存储器和数据管线之间传递数据。

8. 发明授权

US06571367B1 Method and apparatus connecting between a fiber channel and a cache memory 有权
标题翻译：连接在光纤通道和高速缓冲存储器之间的方法和装置
公开(公告)号：US06571367B1
公开(公告)日：2003-05-27
申请号：US09525648
申请日：2000-03-15
申请人： Oren Mano , Paul C. Wilson
发明人： Oren Mano , Paul C. Wilson
IPC分类号： G06F1110
CPC分类号： G06F11/10
摘要： A method and apparatus for connecting between a serial fibre channel link and a global memory provide a bidirectional high throughput path for enabling reliable communications and translation from the fibre channel format to the format required by the global memory. The apparatus includes, in series from the fibre channel link, a bidirectional physical interface, a bidirectional conversion circuitry for converting between an electrical protocol from the fibre channel and a high speed conventional protocol such as a PCI bus, a bidirectional lower machine controlled by a central processing unit and able to add block protection words to the passing data stream, and for separating the data stream into one of a plurality of pipes as directed by the CPU, an error detection and correction circuitry for adding yet additional error correcting data to the data stream as it written in the global memory and for detecting and correcting, if possible, any errors in data being retrieved from global memory. The apparatus further includes dual port random access memories for buffering between the error detection and correction circuitry and the global memory. A secondary port interface is provided, connected to the CPU bus, for providing information to configure at least conversion circuitry.
摘要翻译：用于连接串行光纤通道链路和全局存储器的方法和装置提供双向高吞吐量路径，用于实现从光纤通道格式到全局存储器所需格式的可靠通信和转换。该装置包括从光纤通道链路串联的双向物理接口，用于在来自光纤通道的电气协议和诸如PCI总线的高速常规协议之间进行转换的双向转换电路，由中央处理单元，并且能够向通过的数据流添加块保护字，并且用于将数据流分离成由CPU指导的多个管道中的一个;错误检测和校正电路，用于将附加的纠错数据添加到数据流写入全局存储器中，并且如果可能，则检测和校正从全局存储器检索的数据中的任何错误。该装置还包括用于在错误检测和校正电路与全局存储器之间进行缓冲的双端口随机存取存储器。提供了连接到CPU总线的辅助端口接口，用于提供至少配置转换电路的信息。

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