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1. 发明授权

US6018763A High performance shared memory for a bridge router supporting cache coherency 失效
标题翻译：支持高速缓存一致性的桥接路由器的高性能共享内存
公开(公告)号：US6018763A
公开(公告)日：2000-01-25
申请号：US858182
申请日：1997-05-28
申请人： John H. Hughes , Mark S. Isfeld
发明人： John H. Hughes , Mark S. Isfeld
IPC分类号： G06F12/08 , H04L12/56 , G06F15/167 , G06F15/17
CPC分类号： H04L12/5693 , G06F12/0822 , H04L49/90 , H04L49/901 , H04L49/9047
摘要： An internetwork device manages the flow of packets of I/O data among a plurality of network interface devices. The internetwork device includes an I/O bus which is coupled to the plurality of network interface devices and a shared memory, for storing packets of I/O data and control structures needed by the plurality internetwork interface devices. The shared memory is also coupled to a processor bus, which connects to a processor and a processor memory. The processor memory is isolated from the shared memory, and is used for storing routines and internetworking information involved in routing packets of I/O data among the plurality of network interface devices. In this way, accesses between the processor and the processor memory are decoupled from accesses between the plurality of network interface devices. System performance is improved by storing copies of items from the shared memory in a processor cache located near the processor. Consistency rules are enforced between items in the shared memory and copies of the items in the processor cache through communications across the processor bus. Communications across the processor bus to enforce consistency rules are minimized by maintaining a shadow tag store near the shared memory, which keeps track of the items from the shared memory which are copied in the processor cache. Communications to enforce consistency rules only take place if the shadow tag store indicates that the processor cache contains an item of data from the shared memory which has been read from or written to.
摘要翻译：互联网络设备管理多个网络接口设备之间的I / O数据分组的流。互联网络设备包括耦合到多个网络接口设备的I / O总线和用于存储多个互联网络接口设备所需的I / O数据和控制结构的分组的共享存储器。共享存储器还耦合到处理器总线，其连接到处理器和处理器存储器。处理器存储器与共享存储器隔离，并且用于存储在多个网络接口设备之间路由I / O数据分组中涉及的例程和互联网络信息。以这种方式，处理器和处理器存储器之间的访问与多个网络接口设备之间的访问分离。通过将来自共享存储器的项目副本存储在位于处理器附近的处理器高速缓存器中来提高系统性能。一致性规则在共享存储器中的项目和处理器缓存中的项目的副本之间通过整个处理器总线的通信来执行。通过在共享存储器附近保持阴影标签存储来保持处理器总线上的通信，从而实现一致性规则的最小化，共享存储器可以跟踪共享存储器中复制在处理器高速缓存中的项目。如果影子标签存储指示处理器缓存包含从已经被读取或写入的共享存储器中的数据项，则仅执行用于强制一致性规则的通信。

2. 发明授权

US5664166A System for generating a variable signal in response to a toggle signal selectively delayed using a clock edge and time delay measured from the clock edge 失效
标题翻译：用于响应于使用时钟边缘选择性地延迟的触发信号和从时钟边缘测量的时间延迟来产生可变信号的系统
公开(公告)号：US5664166A
公开(公告)日：1997-09-02
申请号：US438882
申请日：1995-05-10
申请人： Mark S. Isfeld
发明人： Mark S. Isfeld
IPC分类号： G06F1/025 , G06F1/08 , G06F13/16 , G06F1/04 , G06F1/12
CPC分类号： G06F13/1689 , G06F1/025 , G06F1/08
摘要： A digital circuit for generating a signal with a pulse width that is other than a half multiple of the clock is shown. The signal width can be greater or less than the clock period. This digital circuit includes a signal modifier, responsive to the clock signal, for generating a signal with a logic 0 state in response to the first clock edge and a signal with a logic 1 state in response to a toggle signal. A delay circuit generates the toggle signal in response to the second clock edge and a time delay measured from the second clock edge. With the appropriate delay element in the delay circuit, the generating of the toggle signal can be selectively delayed to extend the duration of the pulse.
摘要翻译：示出了用于产生具有不同于时钟的一半倍的脉冲宽度的信号的数字电路。信号宽度可以大于或小于时钟周期。该数字电路包括响应于时钟信号的信号修改器，用于响应于第一时钟沿产生具有逻辑0状态的信号和响应于触发信号的具有逻辑1状态的信号。延迟电路响应于第二时钟沿和从第二时钟沿测量的时间延迟来产生触发信号。利用延迟电路中适当的延迟元件，可以选择性地延迟触发信号的产生以延长脉冲的持续时间。

3. 发明授权

US5646553A Driver for tri-state bus 失效
标题翻译：三态车司机
公开(公告)号：US5646553A
公开(公告)日：1997-07-08
申请号：US438488
申请日：1995-05-10
申请人： Bruce W. Mitchell , Mark S. Isfeld
发明人： Bruce W. Mitchell , Mark S. Isfeld
IPC分类号： G06F13/40 , H03K19/00 , H03K19/0185
CPC分类号： H03K19/0016 , G06F13/4072
摘要： A tri-state synchronous bus driver avoids contention between succeeding cycles by shutting off each device's output enable early, so that it is guaranteed to no longer drive the line by the time any other device begins to drive. Enable activation occurs on a leading edge of the bus clock, and deactivation occurs at a delayed half phase clock edge. A low current bus holding cell is coupled to each bi-directional line to maintain the driven signal value until it can be sampled by a receiving device. This has the advantages that set up time is not eroded by the technique, and that the disable timing is relatively non-critical. The technique is particularly useful in gate array technology as process, temperature, and voltage variation can cause considerable fluctuation in the actual timing of circuits.
摘要翻译：三态同步总线驱动器通过早期关闭每个器件的输出使能来避免后续周期之间的争用，从而保证在任何其他器件开始驱动时不再驱动线路。在总线时钟的前沿启用激活，并且在延迟的半相时钟边沿发生停用。低电流总线保持单元耦合到每个双向线路以维持驱动信号值，直到其被接收装置采样为止。这具有设置时间不被该技术侵蚀的优点，并且禁用定时相对不重要。该技术在门阵列技术中特别有用，因为过程，温度和电压变化可能导致电路的实际时序的相当大的波动。

4. 发明授权

US5828835A High throughput message passing process using latency and reliability classes 失效
标题翻译：使用延迟和可靠性类的高吞吐量消息传递过程
公开(公告)号：US5828835A
公开(公告)日：1998-10-27
申请号：US675663
申请日：1996-07-03
申请人： Mark S. Isfeld , Tracy D. Mallory , Bruce W. Mitchell , Michael J. Seaman , Nagaraj Arunkumar , Pyda Srisuresh
发明人： Mark S. Isfeld , Tracy D. Mallory , Bruce W. Mitchell , Michael J. Seaman , Nagaraj Arunkumar , Pyda Srisuresh
IPC分类号： G06F13/38 , H04L12/46 , H04L12/56 , H04L29/06 , G06F13/00
CPC分类号： H04L49/901 , G06F13/387 , H04L12/4604 , H04L12/5601 , H04L45/00 , H04L47/6215 , H04L49/107 , H04L49/108 , H04L49/256 , H04L49/309 , H04L49/90 , H04L49/9031 , H04L49/9047 , H04L49/9084 , H04L2012/5627 , H04L2012/5651 , H04L2012/5665 , H04L2012/5681 , H04L69/16
摘要： A communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. On the transmit side, a high priority command list and a normal priority command list are provided. In the message passing process, the command transmit function transmits commands across the backplane according to a queue priority rule that allows for control of transmit latency. Messages that require low latency are written into the high priority transmit list, while a majority of messages are written into the high throughput or normal priority transmit list. A receive filtering process in the receiving processor includes dispatch logic which dispatches messages either to a high priority receive list or a normal priority receive list. The filtering function also acts to drop messages received according to the amount of available buffer space in the receiving processor, as measured against watermarks based on reliability tags in message headers. The messages received are routed to either the high priority receive list or a normal priority receive list based on another control bit in the message headers. The receiving processor processes the messages in the receive queues according to a priority rule that allows for control of the latency between receipt of a message, and actual processing of the message by the receiving processor.
摘要翻译：分布式处理系统中用于大容量无连接协议，骨干通信链路的通信技术提供了传输消息的延迟和可靠性的控制。该系统在链路上的处理器中提供发送列表和接收列表过程。在发送侧，提供高优先级命令列表和普通优先级命令列表。在消息传递过程中，命令发送功能根据允许发送等待时间的控制的队列优先级规则跨背板传输命令。需要低延迟的消息被写入高优先级发送列表，而大多数消息被写入高吞吐量或普通优先级发送列表。接收处理器中的接收过滤处理器包括将消息分派到高优先级接收列表或普通优先接收列表的分派逻辑。滤波功能还用于根据基于消息头中的可靠性标签的水印来测量根据接收处理器中的可用缓冲器空间量而接收的消息。接收的消息基于消息头中的另一控制位被路由到高优先级接收列表或普通优先接收列表。接收处理器根据允许控制接收到消息之间的等待时间和接收处理器对消息的实际处理的优先级规则处理接收队列中的消息。

5. 发明授权

US5802278A Bridge/router architecture for high performance scalable networking 失效
标题翻译：用于高性能可扩展网络的桥接/路由器架构
公开(公告)号：US5802278A
公开(公告)日：1998-09-01
申请号：US599473
申请日：1996-01-23
申请人： Mark S. Isfeld , Tracy D. Mallory , Bruce W. Mitchell , Michael J. Seaman , Nagaraj Arunkumar
发明人： Mark S. Isfeld , Tracy D. Mallory , Bruce W. Mitchell , Michael J. Seaman , Nagaraj Arunkumar
IPC分类号： G06F13/38 , H04L12/46 , H04L12/56 , H04L29/06 , G06F15/16 , G06F13/14
CPC分类号： H04L49/901 , G06F13/387 , H04L12/4604 , H04L12/5601 , H04L45/00 , H04L47/6215 , H04L49/107 , H04L49/108 , H04L49/256 , H04L49/309 , H04L49/90 , H04L49/9031 , H04L49/9047 , H04L49/9084 , H04L2012/5627 , H04L2012/5651 , H04L2012/5665 , H04L2012/5681 , H04L69/16
摘要： A high performance scalable networking bridge/router system is based on a backbone communication medium and message passing process which interconnects a plurality of input/output modules. The input/output modules vary in complexity from a simple network interface device having no switching or routing resources on board, to a fully functional bridge/router system. Also, in between these two extremes input/output modules which support distributed protocol processing are supported. A central internetworking engine includes a shared memory resource coupled to the backbone. The architecture includes a physical layer communication system for transferring control messages and data packets across the backbone, a logical layer interprocessor messaging system which operates over the physical layer across the backbone for communication between intelligent input/out modules, and between such modules in the central internetworking engine, and distributed protocol modules which are supported on intelligent input/output modules, and communicate using the logical interprocessor messaging system with the central internetworking resources.
摘要翻译：高性能可扩展网络桥接器/路由器系统基于骨干通信介质和互连多个输入/输出模块的消息传递过程。输入/输出模块的复杂性从一个没有板上交换或路由资源的简单网络接口设备到完全功能的桥接/路由器系统。而且，支持这两种支持分布式协议处理的极端输入/输出模块之间。中央互联网络引擎包括耦合到主干的共享存储器资源。该架构包括用于在骨干网上传输控制消息和数据分组的物理层通信系统，逻辑层处理器消息传递系统，其通过跨骨架的物理层在智能输入/输出模块之间以及在中央的这些模块之间进行操作互联网引擎和智能输入/输出模块支持的分布式协议模块，并使用具有中央互联网资源的逻辑处理器消息系统进行通信。

6. 发明授权

US5471618A System for classifying input/output events for processes servicing the events 失效
标题翻译：用于为服务事件的进程分类输入/输出事件的系统
公开(公告)号：US5471618A
公开(公告)日：1995-11-28
申请号：US982876
申请日：1992-11-30
申请人： Mark S. Isfeld
发明人： Mark S. Isfeld
IPC分类号： G06F13/26
CPC分类号： G06F13/26
摘要： A mixed poll-interrupt system optimizes performance of a processor managing status information indicating the occurrence of service-requiring events generated by I/O devices. Separation logic separates the status information into a first class of more time-critical status indications and a second class of less time-critical status indications. A processor interface is connected to the separation logic and the processor, and stores data identifying status indications in the first class and data identifying status indications in the second class. The processor services the events corresponding to the status indications in the first class with a relatively higher priority routine, such as an interrupt service routine, and services the events corresponding to the status indications in the second class with a relatively lower priority routine, such as a polling routine. The separation logic also includes match logic, which matches addresses or other control information generated by the I/O device, with a prespecified match value which indicates an event having a time-critical need for service. Upon detection of a match, an indication in the first class is generated and serviced by the managing processor with an interrupt service routine.
摘要翻译：混合轮询中断系统优化处理器管理状态信息的性能，指示由I / O设备生成的服务需求事件的发生。分离逻辑将状态信息分为第一类更时间关键的状态指示和第二类较少时间关键的状态指示。处理器接口连接到分离逻辑和处理器，并且存储识别第一类中的状态指示的数据和识别第二类中的状态指示的数据。处理器使用相对较高的优先级例程（例如中断服务程序）来服务与第一类中的状态指示相对应的事件，并且使用相对较低优先级的例程来服务与第二类中的状态指示相对应的事件，例如轮询程序。分离逻辑还包括将由I / O设备产生的地址或其他控制信息与匹配值相匹配的匹配逻辑，该预定匹配值指示具有时间关键性服务需求的事件。在检测到匹配时，通过中断服务程序，由管理处理器生成和维护第一类中的指示。

7. 发明授权

US5592622A Network intermediate system with message passing architecture 失效
标题翻译：具有消息传递架构的网络中间系统
公开(公告)号：US5592622A
公开(公告)日：1997-01-07
申请号：US438897
申请日：1995-05-10
申请人： Mark S. Isfeld , Bruce W. Mitchell , Michael J. Seaman , Tracy D. Mallory , Nagaraj Arunkumar
发明人： Mark S. Isfeld , Bruce W. Mitchell , Michael J. Seaman , Tracy D. Mallory , Nagaraj Arunkumar
IPC分类号： G06F13/38 , H04L12/46 , H04L12/56 , G06F13/00 , G06F15/163
CPC分类号： H04L12/5601 , G06F13/387 , H04L12/4604 , H04L45/00 , H04L49/107 , H04L49/256 , H04L49/309 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9084 , H04L2012/5651 , H04L2012/5665
摘要： A system uses a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router. A bus interconnects the plurality of processors with a plurality of bus interface devices. The bus interface device which originates a transfer includes a command list storing lists of commands which characterize transfers of data messages from local memory across the bus and a packing buffer which buffers the data subject of the command being executed between local memory and the bus. A bus interface device which receives a transfer includes a free buffer list storing pointers to free buffers in local memory into which the data may be loaded from the bus, and a receive list storing pointers to buffers in local memory loaded with data from the bus. The command list includes a first high priority command list and a second lower priority command list for managing latency of the higher priority commands in the software of the processor. The bus interface which receives the transfer includes control logic which manages data transfer into and out of an inbound buffer, including receiving burst transfers of message transfer cells from the bus, loading free buffers in local memory from the inbound buffer with message transtar cells, and updating the receive list. The receive list includes a first higher priority receive list and a second lower priority receive list for reliability management, and logic which monitors the free list so that lower priority messages may be dropped to prevent overflow of free buffer resources.
摘要翻译：系统使用消息传递范例来在诸如网络中间系统或路由器的多个处理器之间传送大量输入/输出数据。总线将多个处理器与多个总线接口设备互连。始发传输的总线接口设备包括命令列表，其存储表示通过总线的本地存储器传输数据消息的命令的列表，以及缓冲在本地存储器和总线之间执行的命令的数据对象的打包缓冲器。接收传送的总线接口装置包括存储指向本地存储器中的空闲缓冲器的空闲缓冲器列表，可从该总线加载数据，以及存储指向本地存储器中缓冲器的指针的接收列表，该缓冲器装载有来自总线的数据。命令列表包括用于管理处理器的软件中较高优先级命令的等待时间的第一高优先级命令列表和第二较低优先级命令列表。接收传输的总线接口包括管理进入和离开入站缓冲器的数据传输的控制逻辑，包括从总线接收消息传送单元的突发传送，从具有消息传送信元的入站缓冲器加载本地存储器中的空闲缓冲器，以及更新接收列表。接收列表包括用于可靠性管理的第一较高优先级接收列表和第二较低优先级接收列表，以及监视空闲列表的逻辑，以便可以丢弃较低优先级的消息以防止空闲缓冲器资源的溢出。

8. 发明授权

US5483640A System for managing data flow among devices by storing data and structures needed by the devices and transferring configuration information from processor to the devices 失效
标题翻译：用于通过存储设备所需的数据和结构并将配置信息从处理器传送到设备来管理设备之间的数据流的系统
公开(公告)号：US5483640A
公开(公告)日：1996-01-09
申请号：US23927
申请日：1993-02-26
申请人： Mark S. Isfeld , Bruce W. Mitchell
发明人： Mark S. Isfeld , Bruce W. Mitchell
IPC分类号： H04L12/861 , G06F13/00
CPC分类号： H04L49/9057 , H04L49/90
摘要： An internetwork device which manages the flow of packets of I/O data among a plurality of network interface devices includes a bus coupled to the plurality of network interface devices, a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices, and a processor including local memory isolated from the core memory storing routines and internetwork information involved in updating control structures and control fields in the packets of I/O data to direct movements of packets of I/O data among the plurality of network interface devices. A bus-memory interface is provided through which transfers of packets of I/O/data and control structures used by the plurality of network interface devices are conducted between the core memory and the bus. A processor-memory interface is provided through which transfers of data to or from control structures or control fields in packets of I/O data are conducted between the core memory and the processor. Finally, a processor-bus interface is included through which configuration information concerning control structures and I/O data buffers in the core memory are transferred between the plurality of network interface devices and the processor across the bus. The processor-bus and processor-memory interfaces include structures for decoupling processor accesses to configuration stores in the plurality network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.
摘要翻译：管理多个网络接口设备之间的I / O数据分组流的互联网络设备包括耦合到多个网络接口设备的总线，仅存储I / O数据分组的核心存储器和由多个网络接口设备，以及包括本地存储器的处理器，所述本地存储器与核心存储器存储存储例程有关，并且涉及更新I / O数据分组中的控制结构和控制字段所涉及的互联网络信息，以引导I / O数据分组的移动多个网络接口设备。提供了一种总线存储器接口，通过该总线存储器接口，在核心存储器和总线之间传输由多个网络接口设备使用的I / O /数据和控制结构的分组。提供了处理器 - 存储器接口，通过该处理器存储器接口在核心存储器和处理器之间传送数据到I / O数据包中的控制结构或控制字段的数据。最后，包括一个处理器总线接口，通过该处理器总线接口，通过该控制结构和核心存储器中的I / O数据缓冲器的配置信息通过总线在多个网络接口设备和处理器之间传送。处理器总线和处理器 - 存储器接口包括用于将处理器访问解耦到多个网络接口设备中的配置存储的结构，以及核心存储器与核心存储器与多个网络接口设备之间的总线存储器接口传输争用的结构。

9. 发明授权

US5459840A Input/output bus architecture with parallel arbitration 失效
标题翻译：具有并行仲裁的输入/输出总线结构
公开(公告)号：US5459840A
公开(公告)日：1995-10-17
申请号：US23008
申请日：1993-02-26
申请人： Mark S. Isfeld , Michael H. Bowman , Niles E. Strohl
发明人： Mark S. Isfeld , Michael H. Bowman , Niles E. Strohl
IPC分类号： G06F13/374 , G06F13/14
CPC分类号： G06F13/374
摘要： A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines. Distributed arbitration logic on each of the interface devices supplies local arbitration codes to a particular line in the set of lines in the arbitration cycle, and detects an arbitration win during the same phase in response to the local arbitration code, and other arbitration codes driven on the set of lines during the arbitration cycle. Each module coupled to the bus also assigned a local priority code. During the arbitration cycle, both the arbitration code and the priority code are driven on respective subsets of the shared sets of lines. Assertion of the local priority code overrides normal requests for the bus. The arbitration logic on each module includes a bus request logic which has the effect of defining arbitration cycles, such that in a particular arbitration phase, a group of modules that asserts a bus request signal controls the bus request signal until all modules in the group have won arbitration.
摘要翻译：适用于基于三总线相位类型的高速互联网应用的高性能总线，包括仲裁阶段，地址阶段和数据阶段。仲裁，地址和数据阶段共享一组单行。每个接口设备上的分布式仲裁逻辑将本地仲裁代码提供给仲裁周期中的一组线路中的特定线路，并且响应于本地仲裁代码在相同阶段期间检测到仲裁胜诉，并且其他仲裁代码被驱动仲裁周期内的一组线路。耦合到总线的每个模块也分配了本地优先级代码。在仲裁周期期间，仲裁代码和优先级代码都是在共享线路组的各个子集上驱动的。断言本地优先级代码将覆盖总线的正常请求。每个模块上的仲裁逻辑包括总线请求逻辑，其具有定义仲裁周期的效果，使得在特定仲裁阶段中，断言总线请求信号的一组模块控制总线请求信号，直到该组中的所有模块具有赢得仲裁

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