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1. 发明授权

US5134616A Dynamic RAM with on-chip ECC and optimized bit and word redundancy 失效
标题翻译：具有片上ECC和优化位和动态冗余的动态RAM
公开(公告)号：US5134616A
公开(公告)日：1992-07-28
申请号：US479145
申请日：1990-02-13
申请人： John E. Barth, Jr. , Charles E. Drake , John A. Fifield , William P. Hovis , Howard L. Kalter , Scott C. Lewis , Daniel J. Nickel , Charles H. Stapper , James A. Yankosky
发明人： John E. Barth, Jr. , Charles E. Drake , John A. Fifield , William P. Hovis , Howard L. Kalter , Scott C. Lewis , Daniel J. Nickel , Charles H. Stapper , James A. Yankosky
IPC分类号： G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

2. 发明授权

US4999815A Low power addressing systems 失效
标题翻译：低功耗寻址系统
公开(公告)号：US4999815A
公开(公告)日：1991-03-12
申请号：US479137
申请日：1990-02-13
申请人： John E. Barth, Jr. , Charles E. Drake , William P. Hovis , Howard L. Kalter , Gordon A. Kelley, Jr. , Scott C. Lewis , Daniel J. Nickel , James A. Yankosky
发明人： John E. Barth, Jr. , Charles E. Drake , William P. Hovis , Howard L. Kalter , Gordon A. Kelley, Jr. , Scott C. Lewis , Daniel J. Nickel , James A. Yankosky
IPC分类号： G11C11/41 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/401 , G11C11/406
CPC分类号： G11C8/18 , G11C8/10 , G11C8/12
摘要： Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission gate systems being coupled to a different one of the second given number of decoders, and second control circuits for selectively activating the first and second gates of each of the second plurality of transmission gate systems.

3. 发明授权

US5015880A CMOS driver circuit 失效
标题翻译： CMOS驱动电路
公开(公告)号：US5015880A
公开(公告)日：1991-05-14
申请号：US419341
申请日：1989-10-10
申请人： Charles E. Drake , Howard L. Kalter , Scott C. Lewis
发明人： Charles E. Drake , Howard L. Kalter , Scott C. Lewis
IPC分类号： H03K17/687 , H03K17/04 , H03K19/003 , H03K19/017 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/01721
摘要： A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned "on" and "off" by the input node to supply an output signal to the output node when turned "on". A second transistor is provided, the output of which is connected to the output node when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor; however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor will cause the second transistor to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

4. 发明授权

US5241500A Method for setting test voltages in a flash write mode 失效
标题翻译：在闪写中设置测试电压的方法
公开(公告)号：US5241500A
公开(公告)日：1993-08-31
申请号：US922597
申请日：1992-07-29
申请人： John E. Barth, Jr. , Howard L. Kalter
发明人： John E. Barth, Jr. , Howard L. Kalter
IPC分类号： G11C11/401 , G11C7/20 , G11C8/12 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/50
CPC分类号： G11C29/50 , G11C29/14 , G11C29/34 , G11C7/20 , G11C8/12 , G11C16/04
摘要： A method is provided for flash writing to multiple cells of a memory array. Initially, a first set of word lines, each of which controls connection of a memory cell of a first set of memory cells to a first bit line of a bit line pair, is turned on. The voltage between the two bit lines of the bit line pair is then equalized so that the charge on the first bit line of the bit line pair is higher than the charge on the second bit line of the bit line pair. Next, a sense amplifier attached to the bit line pair is turned on to sense a difference in charge between the bit line pair and to charge the first set of memory cells. Then a second set of word lines, each of which controls connection of a memory cell of a second set of memory cells to the second bit line is turned on. Finally, the word lines previously turned on are shut off and then the sense amplifier is shut off. Additionally, an apparatus is provided which allows for: turning on multiple word lines at one time, keeping an equalization means on until after at least one set of word lines have gone on, and controlling the operation of the sense amplifier to turn on and shut off at appropriate times.
摘要翻译：提供了一种用于闪存写入存储器阵列的多个单元的方法。最初，将第一组字线控制第一组存储器单元的存储单元与位线对的第一位线的连接。然后，位线对的两个位线之间的电压被均衡，使得位线对的第一位线上的电荷高于位线对的第二位线上的电荷。接下来，连接到位线对的读出放大器导通，以感测位线对之间的电荷差，并对第一组存储器单元充电。然后，第二组字线，其中的每一个控制第二组存储器单元的存储单元与第二位线的连接。最后，关闭以前打开的字线，然后关闭读出放大器。此外，提供了一种装置，其允许：一次打开多个字线，保持均衡装置开启，直到在至少一组字线已经过去之后，并且控制读出放大器的操作以导通和关闭在适当的时候关闭。

5. 发明授权

US5581567A Dual level error detection and correction employing data subsets from previously corrected data 失效
标题翻译：采用来自先前校正的数据的数据子集进行双电平误差检测和校正
公开(公告)号：US5581567A
公开(公告)日：1996-12-03
申请号：US401297
申请日：1995-03-09
申请人： Chin-Long Chen , John A. Fifield , Howard L. Kalter , Willem B. van der Hoeven
发明人： Chin-Long Chen , John A. Fifield , Howard L. Kalter , Willem B. van der Hoeven
IPC分类号： G06F11/10 , G06F12/16 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1008
摘要： A memory system that provides extra data bits without utilizing storage capacity. A first data word is fetched from memory and corrected to remove any single-bit errors. A second data word (which is a subset of the first data word as corrected) is then fetched, and new data correction bits (parity or ECC check bits) is generated for the second data word. Both the second data word and the newly-generated data correction bits are output. This structure amortizes the expense of in-system data correction over a greater data output, and over a smaller storage capacity relative to the data output.
摘要翻译：一种提供额外数据位而不占用存储容量的存储器系统。从存储器中取出第一个数据字，并进行纠正以消除任何单位错误。然后取出第二数据字（其是被校正的第一数据字的子集），并且为第二数据字生成新的数据校正位（奇偶校验位或ECC校验位）。输出第二数据字和新产生的数据校正位。该结构通过更大的数据输出和相对于数据输出的较小的存储容量来摊销系统内数据校正的费用。

6. 发明授权

US5533036A Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
标题翻译：容错计算机存储器系统和采用双级错误校正和检测功能的组件
公开(公告)号：US5533036A
公开(公告)日：1996-07-02
申请号：US486628
申请日：1995-06-07
申请人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter
发明人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
摘要翻译：在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个存储器单元都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正能力的装置来增强存储器可靠性例如，响应于在一个存储器单元中出现不可校正的错误。这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

7. 发明授权

US5031151A Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty 失效
标题翻译：字线驱动禁止电路实现世界线冗余，而无需访问时间损失
公开(公告)号：US5031151A
公开(公告)日：1991-07-09
申请号：US600944
申请日：1990-10-22
申请人： John A. Fifield , Howard L. Kalter , Christopher P. Miller , Steven W. Thomashot
发明人： John A. Fifield , Howard L. Kalter , Christopher P. Miller , Steven W. Thomashot
IPC分类号： G11C29/00
CPC分类号： G11C29/84
摘要： A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available to each of a plurality of sub-arrays of normal memory.
摘要翻译：描述了在不影响访问时间的情况下实现字线冗余的半导体存储器件。冗余解码器电路产生禁止产生正常字线信号的字线驱动禁止信号。取消选择也取消选择通常访问的参考单元，要求冗余单元提供自己的参考信号。最后一个要求是通过利用双电池来实现冗余存储器。将冗余存储器单元放置在位线隔离器的感测节点侧使得能够有效地加倍可用于正常存储器的多个子阵列中的每一个的冗余单元。

8. 发明授权

US5010524A Crosstalk-shielded-bit-line dram 失效
标题翻译：串扰屏蔽位线
公开(公告)号：US5010524A
公开(公告)日：1991-04-23
申请号：US340962
申请日：1989-04-20
申请人： John A. Fifield , Howard L. Kalter
发明人： John A. Fifield , Howard L. Kalter
IPC分类号： G11C11/401 , G11C7/18 , G11C11/4097
CPC分类号： G11C11/4097 , G11C7/18
摘要： This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines associated with a common sense amplifier. One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

9. 发明授权

US06177809B1 Redundant input/output driver circuit 失效
标题翻译：冗余输入/输出驱动电路
公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译：由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态状态的第一个片外驱动电路。

10. 发明授权

US5228046A Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
标题翻译：容错计算机存储器系统和采用双级错误校正和检测功能的组件
公开(公告)号：US5228046A
公开(公告)日：1993-07-13
申请号：US790797
申请日：1991-11-12
申请人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter
发明人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
摘要翻译：在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级纠错能力，并且每个存储单元都与系统级错误校正功能相关联，通过提供用于禁用单位级错误校正的机制来增强存储器可靠性能力，例如，响应于在一个存储器单元中发生不可校正的错误。这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

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