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1. 发明申请

US20090321805A1 INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE 审中-公开
标题翻译：绝缘导线上的绝缘材料
公开(公告)号：US20090321805A1
公开(公告)日：2009-12-31
申请号：US12165072
申请日：2008-06-30
申请人： Johannes von Kluge , Arnd Scholz , Joerg Radecker , Matthias Patz , Stephan Kudelka , Alejandro Avellan
发明人： Johannes von Kluge , Arnd Scholz , Joerg Radecker , Matthias Patz , Stephan Kudelka , Alejandro Avellan
IPC分类号： H01L27/108 , H01L29/78 , H01L21/28 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/743 , H01L27/10876 , H01L27/10891 , H01L29/66621
摘要： One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括布置在半导体主体中的凹槽中的导线。绝缘材料设置在导线上。该绝缘材料包括包括水平部分的第一绝缘层和设置在第一绝缘层上的第二绝缘层。还公开了其它方法，装置和系统。

2. 发明申请

US20140051227A1 METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DRY CHEMICAL REMOVAL PROCESS 有权
标题翻译：通过实施干式化学除去工艺形成半导体器件的隔离结构的方法
公开(公告)号：US20140051227A1
公开(公告)日：2014-02-20
申请号：US13584981
申请日：2012-08-14
申请人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
发明人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/02065 , H01L21/31053 , H01L21/31116
摘要： A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.
摘要翻译：一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

3. 发明授权

US07052970B2 Method for producing insulator structures including a main layer and a barrier layer 有权
标题翻译：用于制造包括主层和阻挡层的绝缘体结构的方法
公开(公告)号：US07052970B2
公开(公告)日：2006-05-30
申请号：US10798863
申请日：2004-03-12
申请人： Joerg Radecker
发明人： Joerg Radecker
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： In order to produce insulator structures (8), insulator trenches (21) with aspect ratios of greater than 4:1 are introduced into a semiconductor substrate (1) from a substrate surface (10) and filled with an insulator filling (3). The insulator filling (3) is formed from a plurality of portions (31, 32, 33, 34) which are deposited successively in situ in an HDP/CVD process chamber in the course of an HDP/CVD deposition process. A main layer (33) is provided made from fluorine-doped silicon oxide with good filling properties. A barrier layer (32) is formed directly before the deposition of the main layer (33), said barrier layer preventing an outgassing of the fluorine from the fluorine-doped silicon oxide (33), an interaction of the fluorine with the semiconductor substrate (1) and a formation of defect areas (6) with oxide of low quality in the area of the insulator filling (3). The barrier (32) makes it possible to form nondegrading p-channel transistors (73) in the area of the substrate surface (10). An additional layer (31) and a termination layer (34) respectively effect an adaptation and linking of the main layer (33) and of the barrier layer (32) to preceeding and succeeding process steps.
摘要翻译：为了制造绝缘体结构（8），纵横比大于4:1的绝缘体沟槽（21）从衬底表面（10）引入到半导体衬底（1）中，并填充有绝缘体填充物（3）。绝缘体填充物（3）由多个部分（31,32,33,34）形成，这些部分在HDP / CVD沉积过程中在HDP / CVD处理室中原位沉积。由氟掺杂氧化硅制成的主层（33）具有良好的填充性能。阻挡层（32）直接在主层（33）的沉积之前形成，所述阻挡层防止氟从氟掺杂氧化硅（33）中脱气，氟与半导体衬底的相互作用（ 1）和在绝缘体填充区域（3）中形成具有低质量的氧化物的缺陷区域（6）。屏障（32）使得可以在衬底表面（10）的区域中形成非劣化的p沟道晶体管（73）。附加层（31）和终止层（34）分别影响主层（33）和阻挡层（32）的适配和链接到前面和后续的处理步骤。

4. 发明授权

US08569143B2 Methods of fabricating a semiconductor IC having a hardened shallow trench isolation (STI) 有权
标题翻译：制造具有硬化浅沟槽隔离（STI）的半导体IC的方法
公开(公告)号：US08569143B2
公开(公告)日：2013-10-29
申请号：US13167558
申请日：2011-06-23
申请人： Thorsten Kammler , Joerg Radecker , Christof Streck
发明人： Thorsten Kammler , Joerg Radecker , Christof Streck
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.
摘要翻译：提供用于制造具有硬化浅沟槽隔离（STI）的半导体IC的方法。根据一个实施例，该方法包括提供半导体衬底并形成具有暴露半导体衬底的一部分的开口的蚀刻掩模。蚀刻暴露部分以形成延伸到半导体衬底中的沟槽，并且沉积氧化物以至少部分地填充沟槽。至少氧化物的表面部分被等离子体氮化以形成氮化氧化物层，然后去除蚀刻掩模。

5. 发明申请

US20120302037A1 Method of Protecting STI Structures From Erosion During Processing Operations 有权
标题翻译：保护STI结构防止加工操作过程中侵蚀的方法
公开(公告)号：US20120302037A1
公开(公告)日：2012-11-29
申请号：US13115270
申请日：2011-05-25
申请人： Hans-Juergen Thees , Stephan Kronholz , Joerg Radecker
发明人： Hans-Juergen Thees , Stephan Kronholz , Joerg Radecker
IPC分类号： H01L21/762
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807 , H01L21/823842 , H01L21/84 , H01L27/10894 , H01L27/1203
摘要： Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.
摘要翻译：通常，本公开涉及一种在制造期间至少减少半导体器件的隔离结构的不希望的侵蚀的方法。所公开的一种说明性方法包括在半导体衬底中形成隔离结构，并在多个隔离结构之上形成导电保护环。

6. 发明申请

US20080315326A1 Method for forming an integrated circuit having an active semiconductor device and integrated circuit 审中-公开
标题翻译：用于形成具有有源半导体器件和集成电路的集成电路的方法
公开(公告)号：US20080315326A1
公开(公告)日：2008-12-25
申请号：US11821274
申请日：2007-06-21
申请人： Werner Graf , Ines Uhlig , Daniel Koehler , Joerg Radecker , Lars Heineck
发明人： Werner Graf , Ines Uhlig , Daniel Koehler , Joerg Radecker , Lars Heineck
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L27/10873 , H01L21/3083 , H01L21/31144 , H01L27/10867 , H01L27/10894
摘要： An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.
摘要翻译：具有有源半导体器件的集成电路形成包括由先前形成的导体线限定的沟槽。

7. 发明申请

US20080230839A1 Method of producing a semiconductor structure 审中-公开
标题翻译：半导体结构的制造方法
公开(公告)号：US20080230839A1
公开(公告)日：2008-09-25
申请号：US11728196
申请日：2007-03-23
申请人： Joern Regul , Joerg Radecker , Olaf Storbeck , Kristin Schupke , Tobias Mono
发明人： Joern Regul , Joerg Radecker , Olaf Storbeck , Kristin Schupke , Tobias Mono
IPC分类号： H01L29/76 , H01L21/44 , H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247 , H01L29/6656
摘要： The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals.
摘要翻译：本发明涉及一种制造半导体结构的方法，包括以下步骤：制造栅极叠层结构并氧化至少一部分栅叠层结构的侧壁，其中氧化步骤在低于500℃的温度下进行使用包含氧自由基的工艺气体。

8. 发明授权

US08722479B2 Method of protecting STI structures from erosion during processing operations 有权
标题翻译：保护STI结构免受加工作业侵蚀的方法
公开(公告)号：US08722479B2
公开(公告)日：2014-05-13
申请号：US13115270
申请日：2011-05-25
申请人： Hans-Juergen Thees , Stephan Kronholz , Joerg Radecker
发明人： Hans-Juergen Thees , Stephan Kronholz , Joerg Radecker
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807 , H01L21/823842 , H01L21/84 , H01L27/10894 , H01L27/1203
摘要： Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.
摘要翻译：通常，本公开涉及一种在制造期间至少减少半导体器件的隔离结构的不希望的侵蚀的方法。所公开的一种说明性方法包括在半导体衬底中形成隔离结构，并在多个隔离结构之上形成导电保护环。

9. 发明授权

US08716102B2 Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process 有权
标题翻译：通过干式化学去除方法形成半导体器件隔离结构的方法
公开(公告)号：US08716102B2
公开(公告)日：2014-05-06
申请号：US13584981
申请日：2012-08-14
申请人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
发明人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
IPC分类号： H01L27/092
CPC分类号： H01L21/76224 , H01L21/02065 , H01L21/31053 , H01L21/31116
摘要： A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.
摘要翻译：一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

10. 发明授权

US08603895B1 Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence 有权
标题翻译：通过执行沉积蚀刻沉积顺序形成半导体器件的隔离结构的方法
公开(公告)号：US08603895B1
公开(公告)日：2013-12-10
申请号：US13610263
申请日：2012-09-11
申请人： Frank Jakubowski , Joerg Radecker , Ralf Willecke
发明人： Frank Jakubowski , Joerg Radecker , Ralf Willecke
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： In one example, the method includes forming a patterned etch mask above a semiconducting substrate, performing an etching process through the patterned etch mask to thereby form a trench in the substrate, performing a first deposition process to form a first layer of insulating material above the patterned etch mask and in the trench, and performing an etching process on the first layer of insulating material such that the post-etch thickness of the first layer of insulating material is less than an as-deposited thickness of the first layer of insulating material. The method also includes performing a second deposition process to form a second layer of insulating material on the etched first layer of insulating material, wherein the second layer of insulating material overfills the trench, and removing portions of the etched first layer of insulating material and the second layer of insulating material positioned above the patterned etch mask.
摘要翻译：在一个示例中，该方法包括在半导体衬底上形成图案化蚀刻掩模，通过图案化蚀刻掩模执行蚀刻工艺，从而在衬底中形成沟槽，执行第一沉积工艺以形成第一层绝缘材料图案化的蚀刻掩模和在沟槽中，并且对第一绝缘材料层进行蚀刻处理，使得第一绝缘材料层的后蚀刻厚度小于第一绝缘材料层的沉积厚度。该方法还包括执行第二沉积工艺以在蚀刻的第一绝缘材料层上形成第二绝缘材料层，其中第二绝缘材料层超过沟槽，以及去除蚀刻的第一绝缘材料层的部分和位于图案化蚀刻掩模上方的第二绝缘材料层。

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