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1. 发明申请

US20140051227A1 METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DRY CHEMICAL REMOVAL PROCESS 有权
标题翻译：通过实施干式化学除去工艺形成半导体器件的隔离结构的方法
公开(公告)号：US20140051227A1
公开(公告)日：2014-02-20
申请号：US13584981
申请日：2012-08-14
申请人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
发明人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/02065 , H01L21/31053 , H01L21/31116
摘要： A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.
摘要翻译：一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

2. 发明授权

US08716102B2 Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process 有权
标题翻译：通过干式化学去除方法形成半导体器件隔离结构的方法
公开(公告)号：US08716102B2
公开(公告)日：2014-05-06
申请号：US13584981
申请日：2012-08-14
申请人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
发明人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
IPC分类号： H01L27/092
CPC分类号： H01L21/76224 , H01L21/02065 , H01L21/31053 , H01L21/31116
摘要： A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.
摘要翻译：一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

3. 发明授权

US08603895B1 Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence 有权
标题翻译：通过执行沉积蚀刻沉积顺序形成半导体器件的隔离结构的方法
公开(公告)号：US08603895B1
公开(公告)日：2013-12-10
申请号：US13610263
申请日：2012-09-11
申请人： Frank Jakubowski , Joerg Radecker , Ralf Willecke
发明人： Frank Jakubowski , Joerg Radecker , Ralf Willecke
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： In one example, the method includes forming a patterned etch mask above a semiconducting substrate, performing an etching process through the patterned etch mask to thereby form a trench in the substrate, performing a first deposition process to form a first layer of insulating material above the patterned etch mask and in the trench, and performing an etching process on the first layer of insulating material such that the post-etch thickness of the first layer of insulating material is less than an as-deposited thickness of the first layer of insulating material. The method also includes performing a second deposition process to form a second layer of insulating material on the etched first layer of insulating material, wherein the second layer of insulating material overfills the trench, and removing portions of the etched first layer of insulating material and the second layer of insulating material positioned above the patterned etch mask.
摘要翻译：在一个示例中，该方法包括在半导体衬底上形成图案化蚀刻掩模，通过图案化蚀刻掩模执行蚀刻工艺，从而在衬底中形成沟槽，执行第一沉积工艺以形成第一层绝缘材料图案化的蚀刻掩模和在沟槽中，并且对第一绝缘材料层进行蚀刻处理，使得第一绝缘材料层的后蚀刻厚度小于第一绝缘材料层的沉积厚度。该方法还包括执行第二沉积工艺以在蚀刻的第一绝缘材料层上形成第二绝缘材料层，其中第二绝缘材料层超过沟槽，以及去除蚀刻的第一绝缘材料层的部分和位于图案化蚀刻掩模上方的第二绝缘材料层。

4. 发明申请

US20130020656A1 HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION 有权
标题翻译：高性能HKMG堆栈进行第一次整合
公开(公告)号：US20130020656A1
公开(公告)日：2013-01-24
申请号：US13185112
申请日：2011-07-18
申请人： Frank Jakubowski , Peter Baars , Till Schloesser
发明人： Frank Jakubowski , Peter Baars , Till Schloesser
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/4966 , H01L29/7833
摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.
摘要翻译：半导体器件在功函数层与多晶硅之间形成硅化物界面。实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成硅化物上的多晶硅层。实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

5. 发明申请

US20080026530A1 Method of forming a doped portion of a semiconductor and method of forming a transistor 失效
标题翻译：形成半导体的掺杂部分的方法和形成晶体管的方法
公开(公告)号：US20080026530A1
公开(公告)日：2008-01-31
申请号：US11493028
申请日：2006-07-26
申请人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
发明人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26586 , H01L29/1045
摘要： A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.
摘要翻译：形成半导体衬底的掺杂部分的方法包括：在衬底表面上限定多个突起部分，突出部分具有最小高度; 在衬底表面上提供图案层; 从预定的基板部分去除图案层的部分; 执行离子注入过程，使得离子相对于衬底表面的角度小于90°，其中离子被图案层和突出部分停止，因此预定的衬底部分被掺杂了离子; 并去除图案层。

6. 发明授权

US07078748B2 Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the same 失效
标题翻译：包括用于FET器件的金属层的多层栅极堆栈结构及其制造方法
公开(公告)号：US07078748B2
公开(公告)日：2006-07-18
申请号：US10865763
申请日：2004-06-14
申请人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
发明人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
IPC分类号： H01L27/148
CPC分类号： H01L21/28044
摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.
摘要翻译：通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中，过渡金属是钛，钽或钴。对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。在将多晶硅层图案化之前打开氮化物衬垫。作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

7. 发明授权

US08722523B2 Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure 有权
标题翻译：半导体器件包括自对准接触元件和替换栅电极结构
公开(公告)号：US08722523B2
公开(公告)日：2014-05-13
申请号：US13371049
申请日：2012-02-10
申请人： Till Schloesser , Peter Baars , Frank Jakubowski
发明人： Till Schloesser , Peter Baars , Frank Jakubowski
IPC分类号： H01L29/772
CPC分类号： H01L29/78 , H01L21/28518 , H01L21/28525 , H01L21/288 , H01L21/76816 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.
摘要翻译：当形成包括高k金属栅电极结构的复杂半导体器件时，可以使用升高的漏极和源极配置来控制在执行替代栅极接近时的高度，从而为形成接触元件提供优越的条件，并且还获得良好可控的减小的门高。

8. 发明授权

US08679940B2 Methods for fabricating semiconductor devices with isolation regions having uniform stepheights 有权
标题翻译：用于制造具有均匀步长的隔离区域的半导体器件的方法
公开(公告)号：US08679940B2
公开(公告)日：2014-03-25
申请号：US13399727
申请日：2012-02-17
申请人： Frank Jakubowski , Jörg Radecker , Frank Ludwig
发明人： Frank Jakubowski , Jörg Radecker , Frank Ludwig
IPC分类号： H01L21/302
CPC分类号： H01L21/02065 , H01L21/76224 , H01L21/76283 , H01L29/0657
摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.
摘要翻译：提供制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括形成覆盖半导体衬底的平坦化阻挡层。通过平坦化阻挡层蚀刻沟槽并进入半导体衬底并填充隔离材料。隔离材料被平坦化以建立与平坦化停止层共面的隔离材料的顶表面。在该方法中，进行干燥脱气处理以去除平坦化停止层的一部分和隔离材料的一部分，以将隔离材料的顶表面降低到半导体衬底之上所需的高度级。

9. 发明申请

US20120280296A1 Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same 有权
标题翻译：具有与位于非存储器区域中的栅电极相同材料的DRAM位线的半导体器件及其制造方法
公开(公告)号：US20120280296A1
公开(公告)日：2012-11-08
申请号：US13099692
申请日：2011-05-03
申请人： Peter Baars , Till Schloesser , Frank Jakubowski
发明人： Peter Baars , Till Schloesser , Frank Jakubowski
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10885
摘要： Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.
摘要翻译：通常，本公开涉及一种具有由与器件的非存储区域中的栅电极相同的材料制成的DRAM位线的半导体器件及其制造方法。本文公开的一种说明性方法包括形成包括存储器阵列和逻辑区域的半导体器件。所述方法还包括在所述存储器阵列中形成掩埋字线，并且在形成所述掩埋字线之后，执行第一公共处理操作以形成所述逻辑区域中的导电栅电极的至少一部分并且形成至少一部分的存储器阵列中的导电位线。

10. 发明授权

US07618867B2 Method of forming a doped portion of a semiconductor and method of forming a transistor 失效
标题翻译：形成半导体的掺杂部分的方法和形成晶体管的方法
公开(公告)号：US07618867B2
公开(公告)日：2009-11-17
申请号：US11493028
申请日：2006-07-26
申请人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
发明人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
IPC分类号： H01L21/336 , H01L21/425 , H01L21/22
CPC分类号： H01L21/823412 , H01L21/26586 , H01L29/1045
摘要： A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.
摘要翻译：形成半导体衬底的掺杂部分的方法包括：在衬底表面上限定多个突出部分，突出部分具有最小高度; 在衬底表面上提供图案层; 从预定的基板部分去除图案层的部分; 执行离子注入过程，使得离子相对于衬底表面的角度小于90°，其中离子被图案层和突出部分停止，因此预定的衬底部分被掺杂了离子; 并去除图案层。

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