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1. 发明申请

US20090321805A1 INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE 审中-公开
标题翻译：绝缘导线上的绝缘材料
公开(公告)号：US20090321805A1
公开(公告)日：2009-12-31
申请号：US12165072
申请日：2008-06-30
申请人： Johannes von Kluge , Arnd Scholz , Joerg Radecker , Matthias Patz , Stephan Kudelka , Alejandro Avellan
发明人： Johannes von Kluge , Arnd Scholz , Joerg Radecker , Matthias Patz , Stephan Kudelka , Alejandro Avellan
IPC分类号： H01L27/108 , H01L29/78 , H01L21/28 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/743 , H01L27/10876 , H01L27/10891 , H01L29/66621
摘要： One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括布置在半导体主体中的凹槽中的导线。绝缘材料设置在导线上。该绝缘材料包括包括水平部分的第一绝缘层和设置在第一绝缘层上的第二绝缘层。还公开了其它方法，装置和系统。

2. 发明授权

US07888230B2 Method of making an integrated circuit including structuring a material 有权
标题翻译：制造包括构造材料的集成电路的方法
公开(公告)号：US07888230B2
公开(公告)日：2011-02-15
申请号：US12121331
申请日：2008-05-15
申请人： Johannes von Kluge
发明人： Johannes von Kluge
IPC分类号： H01L21/20
CPC分类号： H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L27/10852 , Y10T428/24612
摘要： A method of making an integrated circuit including structuring a material. The method includes providing an arrangement of three-dimensional bodies. The material is arranged between the bodies and structured directed radiation. The projection pattern of the three-dimensional bodies is transferred into the material. The structured material connects at least two of the three-dimensional bodies.
摘要翻译：制造包括构造材料的集成电路的方法。该方法包括提供三维体的布置。材料布置在主体和结构化定向辐射之间。三维体的投影图案被转移到材料中。结构化材料连接至少两个三维体。

3. 发明申请

US20090176368A1 MANUFACTURING METHOD FOR AN INTEGRATED CIRCUIT STRUCTURE COMPRISING A SELECTIVELY DEPOSITED OXIDE LAYER 审中-公开
标题翻译：用于包含选择性沉积氧化物层的集成电路结构的制造方法
公开(公告)号：US20090176368A1
公开(公告)日：2009-07-09
申请号：US11970673
申请日：2008-01-08
申请人： Nan Wu , Hans Lindemann , Johannes von Kluge
发明人： Nan Wu , Hans Lindemann , Johannes von Kluge
IPC分类号： H01L21/44
CPC分类号： H01L21/7682 , H01L27/105 , H01L27/1052 , H01L29/66795 , H01L29/785
摘要： The present invention provides a manufacturing method for an integrated circuit structure comprising a selectively deposited oxide layer. An integrated circuit structure including a first and second region is provided, the first region being a metal region and the second region being a non-metal region. Then an oxide layer is selectively depositing on the first and second regions. The oxide layer forms a first thickness on the first region and a second thickness on the second region, the first thickness being larger than the second thickness.
摘要翻译：本发明提供一种用于集成电路结构的制造方法，其包括选择性沉积的氧化物层。提供包括第一和第二区域的集成电路结构，第一区域是金属区域，第二区域是非金属区域。然后氧化物层选择性地沉积在第一和第二区域上。氧化物层在第一区域上形成第一厚度，在第二区域上形成第二厚度，第一厚度大于第二厚度。

4. 发明申请

US20080061322A1 Transistor, memory cell array and method of manufacturing a transistor 失效
标题翻译：晶体管，存储单元阵列及制造晶体管的方法
公开(公告)号：US20080061322A1
公开(公告)日：2008-03-13
申请号：US11517557
申请日：2006-09-08
申请人： Johannes von Kluge
发明人： Johannes von Kluge
IPC分类号： H01L29/76
CPC分类号： H01L29/66621 , H01L27/10876 , H01L2924/0002 , H01L2924/00
摘要： A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface.
摘要翻译：晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道以及栅极电极，以控制在沟道中流动的电流。栅极设置在栅极沟槽中，栅极沟槽限定在半导体衬底的顶表面中。第一和第二源极/漏极区域至少延伸到深度d 1，深度d 1是从衬底的顶表面测量的。栅电极的顶表面设置在半导体衬底的顶表面下方。栅电极的顶表面设置在深度d 2上，该深度d 2小于从衬底表面测量的深度d 1，深度d 2。

5. 发明申请

US20080061320A1 Transistor, Memory Cell Array and Method of Manufacturing a Transistor 失效
标题翻译：晶体管，存储单元阵列和制造晶体管的方法
公开(公告)号：US20080061320A1
公开(公告)日：2008-03-13
申请号：US11851510
申请日：2007-09-07
申请人： Johannes von Kluge , Stefan Tegen
发明人： Johannes von Kluge , Stefan Tegen
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66621 , H01L27/10876 , H01L2924/0002 , H01L2924/00
摘要： A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, wherein the depth d1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d1.
摘要翻译：集成电路的晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道区域以及被配置为控制在沟道中流动的电流的栅电极。栅电极设置在栅极沟槽中，该沟槽限定在半导体衬底的顶表面中。第一和第二源极/漏极区域至少延伸到深度d 1，其中从衬底的顶表面测量深度d 1。栅电极的顶表面设置在半导体衬底的顶表面之下，距离顶表面的距离小于深度d 1。

6. 发明授权

US07763514B2 Method of manufacturing a transistor and memory cell array 失效
标题翻译：制造晶体管和存储单元阵列的方法
公开(公告)号：US07763514B2
公开(公告)日：2010-07-27
申请号：US11851510
申请日：2007-09-07
申请人： Johannes von Kluge , Stefan Tegen
发明人： Johannes von Kluge , Stefan Tegen
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L27/10876 , H01L2924/0002 , H01L2924/00
摘要： A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, wherein the depth d1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d1.
摘要翻译：集成电路的晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道区域以及被配置为控制在沟道中流动的电流的栅电极。栅电极设置在栅极沟槽中，该沟槽限定在半导体衬底的顶表面中。第一和第二源极/漏极区域至少延伸到深度d1，其中从衬底的顶表面测量深度d1。栅电极的顶表面设置在半导体衬底的顶表面之下，距离顶表面的距离小于深度d1。

7. 发明授权

US07612406B2 Transistor, memory cell array and method of manufacturing a transistor 失效
标题翻译：晶体管，存储单元阵列及制造晶体管的方法
公开(公告)号：US07612406B2
公开(公告)日：2009-11-03
申请号：US11517557
申请日：2006-09-08
申请人： Johannes von Kluge
发明人： Johannes von Kluge
IPC分类号： H01L29/768
CPC分类号： H01L29/66621 , H01L27/10876 , H01L2924/0002 , H01L2924/00
摘要： A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface.
摘要翻译：晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道以及栅极电极，以控制在沟道中流动的电流。栅极设置在栅极沟槽中，栅极沟槽限定在半导体衬底的顶表面中。第一和第二源极/漏极区域至少延伸到深度d1，深度d1是从衬底的顶表面测量的。栅电极的顶表面设置在半导体衬底的顶表面下方。栅电极的顶表面设置在深度d2，深度d2小于深度d1，深度d2是从衬底表面测量的。

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