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1. 发明授权

US5434108A Grounding method to eliminate the antenna effect in VLSI process 失效
标题翻译：在VLSI过程中消除天线效应的接地方法
公开(公告)号：US5434108A
公开(公告)日：1995-07-18
申请号：US124647
申请日：1993-09-22
申请人： Joe Ko , Chen-Chiu Hsue
发明人： Joe Ko , Chen-Chiu Hsue
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/465
CPC分类号： H01L21/28123 , H01L21/32136 , H01L21/32137
摘要： A method of subjecting an integrated circuit, having electrically grounded elements and large first metal regions on its surface which are connected to device structures, to a plasma process, is described. Large first metal regions are connected to the electrically grounded elements. The integrated circuit is placed in a chamber for accomplishing the plasma process. The integrated circuit is subjected to the plasma process such that the connecting of the large first metal regions to the electrically grounded elements prevents damage to the device structures. The integrated circuit is removed from the chamber. Finally, the large first metal regions are disconnected from the electrically grounded elements.
摘要翻译：描述了将具有电接地元件的集成电路及其与器件结构连接的表面上的大的第一金属区域进行等离子体处理的方法。大的第一金属区域连接到电接地元件。将集成电路放置在用于完成等离子体处理的室中。对集成电路进行等离子体处理，使得大的第一金属区域与电接地元件的连接防止对器件结构的损坏。集成电路从腔室中取出。最后，大的第一金属区域与电接地元件断开。

2. 发明授权

US5559352A ESD protection improvement 失效
标题翻译： ESD保护改善
公开(公告)号：US5559352A
公开(公告)日：1996-09-24
申请号：US354373
申请日：1994-12-12
申请人： Chen-Chiu Hsue , Joe Ko
发明人： Chen-Chiu Hsue , Joe Ko
IPC分类号： H01L27/02 , H01L29/76
CPC分类号： H01L27/0266
摘要： A method of forming an ESD protection device with reduced breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices. A second insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The second insulating layer is patterned to form contact openings to the active regions. Finally, a third ion implant of a conductivity-imparting dopant, with opposite conductivity from the first and second ion implants, having equal concentration to dopant from the first ion implant, is performed through the contact openings into active regions of the ESD protection device.
摘要翻译：描述了与包括FET器件的集成电路同时形成具有降低的击穿电压的ESD保护器件的方法以及所得到的器件结构。提供硅基板，其上有场氧化物区域，栅极和有源区域。导电性赋予掺杂剂的第一离子注入在垂直方向上进入ESD保护器件和FET器件的有源区。在ESD保护器件和FET器件上以及场氧化物区域上形成第一绝缘层。图案化第一绝缘层以产生与ESD保护器件和FET器件的栅极相邻的间隔物。与来自第一离子注入的掺杂剂相比，具有更高浓度的导电性赋予掺杂剂的第二离子注入被执行到ESD保护器件和FET器件的有源区。在ESD保护器件和FET器件上以及场氧化物区域上形成第二绝缘层。图案化第二绝缘层以形成到活性区的接触开口。最后，通过所述接触开口将与所述第一和第二离子注入相反的具有与所述第一和第二离子注入物相反的导电性的第三离子注入与所述第一离子注入物的掺杂剂相同地进入到所述ESD保护器件的有源区。

3. 发明授权

US5484743A Self-aligned anti-punchthrough implantation process 失效
标题翻译：自对准抗穿透植入工艺
公开(公告)号：US5484743A
公开(公告)日：1996-01-16
申请号：US394587
申请日：1995-02-27
申请人： Joe Ko , Chen-Chiu Hsue
发明人： Joe Ko , Chen-Chiu Hsue
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66583 , H01L29/1083 , H01L29/66537 , H01L29/7833
摘要： The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.
摘要翻译：本发明涉及形成用于超大规模集成器件的改进的MOSFET器件结构的方法。使用离子注入直接在栅极下方形成局部自对准的穿透区域。局部抗穿透区域减小了通道中的耗尽区域的膨胀，从而增加穿透电压。局部抗穿透区域与栅极电极和源极/漏极区域自对准，使得即使对于亚微米器件也保持临界间隔。沟道迁移率不降低，源极和漏极结电容减小。本发明可用于N沟道或P沟道MOSFET器件，以及LDD（轻掺杂漏极）或非LDD器件中。

4. 发明授权

US5374565A Method for ESD protection improvement 失效
标题翻译： ESD保护方法的改进
公开(公告)号：US5374565A
公开(公告)日：1994-12-20
申请号：US139858
申请日：1993-10-22
申请人： Chen-Chiu Hsue , Joe Ko
发明人： Chen-Chiu Hsue , Joe Ko
IPC分类号： H01L27/02 , H01L21/266
CPC分类号： H01L27/0266
摘要： A method of forming an ESD protection device with reduced junction breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices. A second insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The second insulating layer is patterned to form contact openings to the active regions. Finally, a third ion implant of a conductivity-imparting dopant, with opposite conductivity from the first and second ion implants, having equal concentration to dopant from the first ion implant, is performed through the contact openings into active regions of the ESD protection device.
摘要翻译：描述了与包括FET器件的集成电路同时形成具有降低的结击穿电压的ESD保护器件的方法以及所得到的器件结构。提供硅基板，其上有场氧化物区域，栅极和有源区域。导电性赋予掺杂剂的第一离子注入在垂直方向上进入ESD保护器件和FET器件的有源区。在ESD保护器件和FET器件上以及场氧化物区域上形成第一绝缘层。图案化第一绝缘层以产生与ESD保护器件和FET器件的栅极相邻的间隔物。与来自第一离子注入的掺杂剂相比，具有更高浓度的导电性赋予掺杂剂的第二离子注入被执行到ESD保护器件和FET器件的有源区。在ESD保护器件和FET器件上以及场氧化物区域上形成第二绝缘层。图案化第二绝缘层以形成到活性区的接触开口。最后，通过所述接触开口将与所述第一和第二离子注入相反的具有与所述第一和第二离子注入物相反的导电性的第三离子注入与所述第一离子注入物的掺杂剂相同地进入到所述ESD保护器件的有源区。

5. 发明申请

US20060154418A1 METHOD FOR MANUFACTURING ONE-TIME ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY 失效
标题翻译：制造一次性可编程只读存储器的方法
公开(公告)号：US20060154418A1
公开(公告)日：2006-07-13
申请号：US11160176
申请日：2005-06-13
申请人： Ko-Hsing Chang , Tung-Po Chen , Tung-Ming Lai , Chen-Chiu Hsue
发明人： Ko-Hsing Chang , Tung-Po Chen , Tung-Ming Lai , Chen-Chiu Hsue
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/7833
摘要： A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.
摘要翻译：描述了用于制造OTEPROM的方法。在衬底上形成隧道氧化物层，第一导电层，第一图案化掩模层。在衬底中形成沟槽。形成绝缘层以填充沟槽。目的地形成浮栅的第一导电层的一部分被暴露，然后在其上形成覆盖层。去除第一图案化掩模层，然后在衬底上形成第二导电层和第二图案化掩模层。使用第二图案化掩模层和盖层作为掩模形成字线和浮栅。去除第二图案化掩模层，然后在字线和浮栅两侧以及字线和浮栅之间的衬底中形成源极/漏极区。

6. 发明授权

US06495877B1 Metal capacitors with damascene structures and method for forming the same 有权
标题翻译：具有镶嵌结构的金属电容器及其形成方法
公开(公告)号：US06495877B1
公开(公告)日：2002-12-17
申请号：US10024289
申请日：2001-12-21
申请人： Chen-Chiu Hsue , Shyh-Dar Lee
发明人： Chen-Chiu Hsue , Shyh-Dar Lee
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/76807 , H01L21/76816 , H01L23/5223 , H01L28/60 , H01L28/90
摘要： This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer is formed in an insulator and a stop layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.
摘要翻译：本发明提供一种具有镶嵌结构的金属电容器。在形成薄膜电容器之前，通过镶嵌工艺用Cu制造下面的互连，例如第一Cu线和第二Cu线。由绝缘体和停止层形成由与第一Cu线接触的第一金属层，电介质层和第二金属层构成的薄膜电容器。第一Cu镶嵌结构和第二Cu镶嵌结构分别设置在薄膜电容器和第二Cu线上。

7. 发明授权

US06492226B1 Method for forming a metal capacitor in a damascene process 有权
标题翻译：在镶嵌工艺中形成金属电容器的方法
公开(公告)号：US06492226B1
公开(公告)日：2002-12-10
申请号：US09880849
申请日：2001-06-15
申请人： Chen-Chiu Hsue , Shyh-Dar Lee
发明人： Chen-Chiu Hsue , Shyh-Dar Lee
IPC分类号： H01L218264
CPC分类号： H01L28/55 , H01L21/76838 , H01L28/60
摘要： This invention provides a method for forming a metal capacitor in a damascene process. Before the thin-film capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene process. The lower electrode is formed in a dual damascene process, which is also used to form the dual damascene structures comprising wires and plugs. An insulator is disposed to isolate the dual damascene structures with each other. In this dual damascene process, an anti-reflection layer is used and formed on the insulator, and the anti-reflection layer is also used as a hard mask layer, a polishing stop layer and an etching stop layer. Then, another insulator and a metal layer are formed on the anti-reflection layer, and encounter a photolithography step and an etching step to obtain an upper electrode and a capacitor insulator. After forming the metal capacitor, the upper interconnections are fabricated with another dual damascene processes.
摘要翻译：本发明提供了一种在镶嵌工艺中形成金属电容器的方法。在形成薄膜电容器之前，通过镶嵌工艺用Cu金属制造下面的互连。下电极形成为双镶嵌工艺，其也用于形成包括电线和插头的双镶嵌结构。布置绝缘体以将双镶嵌结构彼此隔离。在这种双镶嵌工艺中，在绝缘体上使用并形成防反射层，并且抗反射层也用作硬掩模层，抛光停止层和蚀刻停止层。然后，在防反射层上形成另一绝缘体和金属层，并且经历光刻步骤和蚀刻步骤以获得上电极和电容器绝缘体。在形成金属电容器之后，上互连用另外的双镶嵌工艺制造。

8. 发明授权

US06483142B1 Dual damascene structure having capacitors 有权
标题翻译：具有电容器的双镶嵌结构
公开(公告)号：US06483142B1
公开(公告)日：2002-11-19
申请号：US10108611
申请日：2002-03-27
申请人： Chen-Chiu Hsue , Shyh-Dar Lee
发明人： Chen-Chiu Hsue , Shyh-Dar Lee
IPC分类号： H01L218242
CPC分类号： H01L21/76807 , H01L23/5223 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.
摘要翻译：本发明提供一种具有电容器的双镶嵌结构。在形成薄膜电容器之前，通过镶嵌工艺用Cu金属制造底层互连。电容器通过沉积第一金属层，绝缘体和第二金属层而形成。然后，对堆叠的层进行两次掩模和蚀刻处理以形成薄膜电容器和金属线。在形成电容器之后，通过镶嵌工艺用Cu金属制造上互连。

9. 发明授权

US06410386B1 Method for forming a metal capacitor in a damascene process 有权
标题翻译：在镶嵌工艺中形成金属电容器的方法
公开(公告)号：US06410386B1
公开(公告)日：2002-06-25
申请号：US09881102
申请日：2001-06-15
申请人： Chen-Chiu Hsue , Shyh-Dar Lee , Jen-Hann Tsai
发明人： Chen-Chiu Hsue , Shyh-Dar Lee , Jen-Hann Tsai
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/76807 , H01L21/76838
摘要： A method for forming a metal capacitor in a damascene process is provided. Before the metal capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. The stacked layers are then subjected to a masking process and an etching process to form the thin-film capacitor and the metal wire with the remaining insulator and the remaining second metal layer thereon. The remaining second metal layer located on the metal wire is removed by another masking process and another etching process. After forming the capacitor and the metal wire, the upper interconnections are fabricated with Cu metal by damascene processes.
摘要翻译：提供了一种在镶嵌工艺中形成金属电容器的方法。在形成金属电容器之前，通过镶嵌工艺用Cu金属制造下面的互连。电容器通过沉积第一金属层，绝缘体和第二金属层而形成。然后对堆叠的层进行掩模处理和蚀刻处理，以在其上形成剩余绝缘体和剩余的第二金属层的薄膜电容器和金属线。位于金属线上的剩余的第二金属层通过另一掩模工艺和另一蚀刻工艺被去除。在形成电容器和金属线之后，通过镶嵌工艺用Cu金属制造上部互连。

10. 发明授权

US06391713B1 Method for forming a dual damascene structure having capacitors 失效
标题翻译：用于形成具有电容器的双镶嵌结构的方法
公开(公告)号：US06391713B1
公开(公告)日：2002-05-21
申请号：US09854872
申请日：2001-05-14
申请人： Chen-Chiu Hsue , Shyh-Dar Lee
发明人： Chen-Chiu Hsue , Shyh-Dar Lee
IPC分类号： H01L218242
CPC分类号： H01L23/5223 , H01L21/76807 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： This invention provides a method for forming a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.
摘要翻译：本发明提供一种形成具有电容器的双镶嵌结构的方法。在形成薄膜电容器之前，通过镶嵌工艺用Cu金属制造底层互连。电容器通过沉积第一金属层，绝缘体和第二金属层而形成。然后，对堆叠的层进行两次掩模和蚀刻处理以形成薄膜电容器和金属线。在形成电容器之后，通过镶嵌工艺用Cu金属制造上互连。

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