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1. 发明授权

US07657772B2 Thermally aware integrated circuit 有权
标题翻译：热感知集成电路
公开(公告)号：US07657772B2
公开(公告)日：2010-02-02
申请号：US10366437
申请日：2003-02-13
申请人： Joachim Gerhard Clabes , Michael Stephen Floyd , Paul David Muench , Lawrence Joseph Powell
发明人： Joachim Gerhard Clabes , Michael Stephen Floyd , Paul David Muench , Lawrence Joseph Powell
IPC分类号： G06F1/04 , G06F1/14
CPC分类号： H01L27/0248 , G01K7/425
摘要： An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.
摘要翻译：一种具有温度敏感电路（TSC）的集成电路，用于产生指示TSC附近的衬底温度的信号。集成电路具有被配置为从至少一个TSC接收TSC信号并且将TSC信号转换成指示集成电路的温度的信号的电路。热控制电路将集成电路温度与阈值进行比较，并在温度超过阈值时产生校正动作信号。校正动作信号被提供给校正动作电路，优选地被配置为修改IC的操作以降低接近相应TSC的IC温度。

2. 发明授权

US06195757B1 Method for supporting 1½ cycle data paths via PLL based clock system 失效
标题翻译：通过基于PLL的时钟系统支持1½周期数据路径的方法
公开(公告)号：US06195757B1
公开(公告)日：2001-02-27
申请号：US09013637
申请日：1998-01-26
申请人： Timothy Gerard McNamara , Patrick James Meaney , Paul David Muench , Giacomo Vincent Ingenio
发明人： Timothy Gerard McNamara , Patrick James Meaney , Paul David Muench , Giacomo Vincent Ingenio
IPC分类号： G06F1300
CPC分类号： H03L7/00 , H03L7/06
摘要： A system for improving system cycle time while supporting 1½ cycle data paths with a PLL based clock system using a communication circuit providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode of operation whereby a second longer multi-mode cycle time is obtained to extend the time for evaluation of data on the bi-directional data path between a first chip and a memory circuit.
摘要翻译：一种用于改善系统周期时间的系统，同时利用基于PLL的时钟系统支持1个周期的数据路径，该系统使用提供第一操作模式的通信电路，从而获得第一周期时间，并且允许使用第二操作模式，获得更长的多模周期时间以扩展用于评估第一芯片和存储器电路之间的双向数据路径上的数据的时间

3. 发明授权

US6058488A Method of reducing computer module cycle time 失效
标题翻译：降低计算机模块周期时间的方法
公开(公告)号：US6058488A
公开(公告)日：2000-05-02
申请号：US23176
申请日：1998-02-13
申请人： James Patrick Eckhardt , Paul David Muench , Wiren D. Becker , Timothy Gerard McNamara
发明人： James Patrick Eckhardt , Paul David Muench , Wiren D. Becker , Timothy Gerard McNamara
IPC分类号： H03L1/00 , H03L7/06 , G06F1/04
CPC分类号： H03L7/06 , H03L1/00
摘要： A reduction of multichip module computer system cycle time is achieved by using a voltage regulator for power supply noise attenuation to reduce jitter. The circuit for doing this includes an active filter network circuit for use in the multichip module of a computer system which generates a quiet analog VDD coupled directly to ground by using the low impedance power supply distributions which already exist in the module. The active filter network permits taking the power supply voltage from the module and stepping it down to a voltage needed by a phased lock loop via an active filter, said active filter comprising an op-amplifier and a source follower and a large value on module capacitor for a resistor network. The capacitor and resistor network acts as a filter with a large time constant where noise appearing on VDD,MOD is completely attenuated by this high value capacitor and resistor network part of our active filter network.
摘要翻译：通过使用电压调节器来实现多芯片模块计算机系统周期时间的减少，以减少抖动。用于这样做的电路包括用于计算机系统的多芯片模块中的有源滤波器网络电路，其通过使用已经存在于模块中的低阻抗电源分布产生直接耦合到地的静音模拟VDD。有源滤波器网络允许从模块获取电源电压并通过有源滤波器将其降到相控锁定所需的电压，所述有源滤波器包括运算放大器和源极跟随器以及模块电容器上的大值用于电阻网络。电容器和电阻网络充当具有大时间常数的滤波器，其中出现VDD，MOD的噪声完全被该有源滤波器网络的高值电容器和电阻网络部分衰减。

4. 发明授权

US5905410A Lock/unlock indicator for PLL circuits 失效
标题翻译： PLL电路的锁定/解锁指示灯
公开(公告)号：US5905410A
公开(公告)日：1999-05-18
申请号：US12167
申请日：1998-01-22
申请人： Glenn Edward Holmes , Timothy Gerard McNamara , Paul David Muench
发明人： Glenn Edward Holmes , Timothy Gerard McNamara , Paul David Muench
IPC分类号： H03L7/089 , H03L7/095
CPC分类号： H03L7/095 , H03L7/089 , Y10S331/02
摘要： A lock circuit for indicating a locked/unlocked condition of phased lock loops circuits, which uses a reference clock signal input to a good-cycle counter and to a bad-cycle counter to signal a set/reset latch to output a signal indicating whether or not the phase of the output signal and input clock are in phase. Phase detector inputs are XOR gated to produce a pulse when the phase locked output clock is in a bad cycle indicated by the phase locked output clock not being in-phase with its input clock. Pulses on the XOR gate output on a bad cycle feed a single cycle counter reset circuit. The single cycle counter reset circuit on every cycle resets one of the bad and good counters based on its detection of a bad cycle pulse from the XOR gate. The good-cycle counter's output is to the SET input of the set/reset latch, and the bad-cycle counter's output is to the RESET input of the set/reset latch . We enable specific cycling of both the good and bad counters.
摘要翻译：用于指示锁相环路电路的锁定/解锁状态的锁定电路，其使用输入到良周期计数器的参考时钟信号和坏周期计数器来发信号通知设置/复位锁存器，以输出指示是否或输出信号和输入时钟的相位不同相。当锁相输出时钟处于由锁相输出时钟与其输入时钟不同相指示的不良周期时，相位检测器输入为异或门控以产生脉冲。异或门输出的脉冲在一个坏的周期内输入单周期计数器复位电路。每个周期的单周期计数器复位电路都会根据检测到异或门坏的周期脉冲来重置坏计数器和好的计数器之一。好周期计数器的输出是设置/复位锁存器的SET输入，坏周期计数器的输出是设置/复位锁存器的RESET输入。我们启用了好的和坏的计数器的特定循环。

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