专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07892445B1 Wafer electrical discharge control using argon free dechucking gas 有权
标题翻译：使用无氩脱胶气体进行晶圆放电控制
公开(公告)号：US07892445B1
公开(公告)日：2011-02-22
申请号：US11853968
申请日：2007-09-12
申请人： David Wei , Howard Dang , Masahiro Watanabe , Sean Kang , Kenji Takeshita , Mayumi Block , Stephen Sirard , Eric Hudson
发明人： David Wei , Howard Dang , Masahiro Watanabe , Sean Kang , Kenji Takeshita , Mayumi Block , Stephen Sirard , Eric Hudson
IPC分类号： B44C1/22
CPC分类号： H01L21/67069 , H01L21/6831
摘要： A method of dechucking a wafer, with a low-k dielectric layer, held onto an electrostatic chuck by an electrostatic charge in a plasma chamber is provided. The electrostatic clamping voltage is removed. An essentially argon free dechucking gas is provided into the plasma chamber. A dechucking plasma is formed from the dechucking gas in the plasma chamber. The dechucking plasma is stopped.
摘要翻译：提供了通过在等离子体室中的静电电荷将具有低k电介质层的晶片脱扣保持在静电卡盘上的方法。静电钳位电压被去除。在等离子体室中提供基本上无氩的脱扣气体。从等离子体室中的脱扣气体形成脱扣等离子体。脱扣等离子体停止。

2. 发明申请

US20100232070A1 APPARATUS OF A SLIDER LIMITER FOR PROTECTING READ-WRITE HEAD FROM NON-OPERATIONAL SHOCK IN A HARD DISK DRIVE 失效
标题翻译：用于保护硬盘驱动器中非操作性震动的读写头的滑动限制装置
公开(公告)号：US20100232070A1
公开(公告)日：2010-09-16
申请号：US12402410
申请日：2009-03-11
申请人： Yao-Hsin Huang , Sean Kang , Bill Wang
发明人： Yao-Hsin Huang , Sean Kang , Bill Wang
IPC分类号： G11B5/48
CPC分类号： G11B5/54
摘要： This application discloses a hard disk drive comprising a landing ramp mounted to a disk base including a slider limiter for at least one slider in the hard disk drive to limit movement of the sliders during a non-operational shock event while parked on the loading ramp. Each of the slider limiters includes a clearance zone configured so that when the slider contacts the slider limiter during the non-operational event, the read-write head remains out of contact with the slider limiter. The clearance zone may include a recess and/or a cutout. The clearance zone may include a recess and/or a cutout. The recess may take any shape, for example the recess may be a polygon and/or curved in cross section. The polygon may have at least two sides. The clearance zone may further include a radial bulge to further protect the read-write head during non-operational shock events.
摘要翻译：本申请公开了一种硬盘驱动器，其包括安装到盘基座的着陆斜坡，该盘底座包括用于硬盘驱动器中的至少一个滑动器的滑块限制器，以在停放在装载斜面上的非操作性冲击事件期间限制滑块的移动。每个滑块限制器包括间隙区域，其被配置为使得当滑块在非操作事件期间接触滑块限制器时，读写头保持与滑块限制器不接触。间隙区可以包括凹部和/或切口。间隙区可以包括凹部和/或切口。凹部可以具有任何形状，例如凹部可以是多边形和/或弯曲成横截面。多边形可以具有至少两个边。间隙区域还可以包括径向凸起，以在非操作的冲击事件期间进一步保护读写头。

3. 发明申请

US20160197121A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20160197121A1
公开(公告)日：2016-07-07
申请号：US14984477
申请日：2015-12-30
申请人： Jin-Woo LEE , Youn-Sean KANG , Seung-Jae JUNG , Hyun-Su JU , Masayuki TERAI
发明人： Jin-Woo LEE , Youn-Sean KANG , Seung-Jae JUNG , Hyun-Su JU , Masayuki TERAI
IPC分类号： H01L27/24 , H01L43/08 , H01L43/02 , H01L45/00 , H01L27/22
CPC分类号： H01L27/2463 , H01L27/224 , H01L27/2409 , H01L43/12 , H01L45/1675
摘要： A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.
摘要翻译：可变电阻存储器件包括多个第一导电层图案，多个第一导电层图案上的第二导电层图案，以及包括开关元件和可变电阻元件的多个下单元结构，下单元结构为形成在第一导电层图案和第二导电层图案彼此重叠的交点处。第一导电层图案，第二导电层图案和下单元结构用作存储单元，第一虚设图案结构和第二虚设图案结构之一。第一虚设图形结构形成在第一方向的两个边缘部分上，第一虚设图案结构的第二导电层图案从其下部单元结构的侧壁沿第一方向突出，第二虚设图案结构为形成在第二方向的两个边缘部分上，并且第二虚设图案结构的第一导电层图案在其下面的单元结构的侧壁上沿第二方向突出。由于蚀刻残留导致的可变电阻存储器件的故障可能降低。

4. 发明申请

US20130001754A1 IN-SITU PHOTORESIST STRIP DURING PLASMA ETCHING OF ACTIVE HARD MASK 有权
标题翻译：活动硬掩模等离子体蚀刻中的现场光电子条纹
公开(公告)号：US20130001754A1
公开(公告)日：2013-01-03
申请号：US13607390
申请日：2012-09-07
申请人： Sangjun Cho , Tom Choi , Taejoon Han , Sean Kang , Prabhakara Gopaladasu , Bi-Ming Yen
发明人： Sangjun Cho , Tom Choi , Taejoon Han , Sean Kang , Prabhakara Gopaladasu , Bi-Ming Yen
IPC分类号： H01L21/308 , H01L21/3065 , H01L29/02
CPC分类号： H01L21/3081 , G03F7/427 , H01L21/31138 , H01L21/32139
摘要： A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
摘要翻译：提供了一种用于蚀刻硅层中的特征的方法。在硅层上形成硬掩模层。在硬掩模层上形成光致抗蚀剂层。打开硬掩模层。通过提供剥离气体来剥离光致抗蚀剂层; 通过提供高频RF功率和低频RF功率与剥离气体形成等离子体，其中低频RF功率具有小于50瓦的功率; 并且当剥离光致抗蚀剂层时停止剥离气体。打开硬掩模层和剥离光致抗蚀剂层在相同的室中进行。

5. 发明授权

US08165933B2 Systems, methods, and computer program products for performing item level transaction processing 有权
标题翻译：用于执行项目级别事务处理的系统，方法和计算机程序产品
公开(公告)号：US08165933B2
公开(公告)日：2012-04-24
申请号：US12126707
申请日：2008-05-23
申请人： Eric Dryer , George Miller Abernethy , Ronald Hollander , Lowell Robert Huff , Sean Kang , Clarence E. Lee , Eric Scott Sandoz , Jeffrey Robert Woodside
发明人： Eric Dryer , George Miller Abernethy , Ronald Hollander , Lowell Robert Huff , Sean Kang , Clarence E. Lee , Eric Scott Sandoz , Jeffrey Robert Woodside
IPC分类号： G07B17/00 , G07F19/00
CPC分类号： G06Q40/02 , G06Q40/12
摘要： The present invention provides systems, methods, and computer program products for performing validation and clearance at a transaction item level for transaction received in a batch format. Each transaction of the batch is stored separately in a storage system, such as a logical database. Typically, image data and electronic data for a transaction are stored separately in the storage system and may be linked to each other. Each transaction is separately accessible and/or updateable. Each transaction stored in the storage system is separately analyzed to validate that the transaction is at least balanced. Transactions that determined to be balanced are cleared irrespective of a balance status associated with other transactions associated with the batch of transactions, such that transactions are individually cleared as opposed to being cleared in a batch format.
摘要翻译：本发明提供了用于在交易项目级别执行以批量格式接收的交易的验证和清除的系统，方法和计算机程序产品。批次的每个事务分开存储在诸如逻辑数据库的存储系统中。通常，用于交易的图像数据和电子数据被分别存储在存储系统中并且可以彼此链接。每个交易可以单独访问和/或可更新。存储在存储系统中的每个事务被分开分析，以验证事务至少是平衡的。无论与批次交易相关的其他交易相关联的余额状态如何，都会清除确定为均衡的交易，这样交易将被单独清除，而不是以批量格式清除。

6. 发明申请

US20080314733A1 Methods of and apparatus for reducing amounts of particles on a wafer during wafer de-chucking 有权
标题翻译：在晶片去夹紧期间减少晶片上的颗粒量的方法和装置
公开(公告)号：US20080314733A1
公开(公告)日：2008-12-25
申请号：US11821314
申请日：2007-06-22
申请人： Sangjun Cho , Sean Kang , Tom Choi , Taejoon Han
发明人： Sangjun Cho , Sean Kang , Tom Choi , Taejoon Han
IPC分类号： H05F3/00 , C25B9/00
CPC分类号： H01L21/6833
摘要： Particles are trapped away from a wafer transport zone in a chamber. A first electrode is on one side of the zone. A second electrode is on an opposite side of the zone. A power supply connected across the electrodes establishes an electrostatic field between the electrodes. The field traps particles at the electrodes, away from the zone. For transporting the wafer from the chamber, the second electrode mounts the wafer for processing, and the first electrode is opposite to the second electrode defining a process space. The zone is in the space with a separate part of the space separating the zone from each electrode. Particles are urged away from the wafer by simultaneously terminating plasma processing of the wafer, connecting the second electrode to ground, applying a positive DC potential to the first electrode, and de-chucking the wafer from the second electrode into the zone.
摘要翻译：颗粒被捕获在室中的晶片运输区域。第一电极位于该区域的一侧。第二电极位于该区域的相对侧。跨电极连接的电源在电极之间建立静电场。该场捕获电极处的颗粒，远离该区域。为了从腔室输送晶片，第二电极安装用于处理的晶片，并且第一电极与限定工艺空间的第二电极相对。该区域在空间中，具有将区域与每个电极分离的空间的单独部分。通过同时终止晶片的等离子体处理，将第二电极连接到地，将正的DC电位施加到第一电极，以及将晶片从第二电极去夹紧到区域中，使颗粒离开晶片。

7. 发明申请

US20060011578A1 Low-k dielectric etch 审中-公开
标题翻译：低k电介质蚀刻
公开(公告)号：US20060011578A1
公开(公告)日：2006-01-19
申请号：US10892945
申请日：2004-07-16
申请人： Sean Kang , Zhisong Huang , S. M. Sadjadi
发明人： Sean Kang , Zhisong Huang , S. M. Sadjadi
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method for etching a dielectric layer below a photoresist mask is provided. A wafer with the dielectric layer disposed below a photoresist mask is provided in an etch chamber. An etch gas comprising CF4 and H2 is provided into the etch chamber wherein the CF4 has a flow rate and the H2 has a flow rate, wherein the flow rate of H2 is greater than the flow rate of CF4. A plasma is formed from the etch gas. Features are etched into the dielectric layer through the etch mask using the plasma formed from the etch gas.
摘要翻译：提供了一种用于蚀刻光致抗蚀剂掩模下面的介电层的方法。在蚀刻室中提供具有设置在光致抗蚀剂掩模下方的介电层的晶片。包括CF 4和H 2 2的蚀刻气体被提供到蚀刻室中，其中CF 4具有流速，并且H 2 2 具有流速，其中H 2 2的流速大于CF 4的流速。由蚀刻气体形成等离子体。通过蚀刻掩模使用由蚀刻气体形成的等离子体将特征蚀刻到介电层中。

8. 发明授权

US06909195B2 Trench etch process for low-k dielectrics 有权
公开(公告)号：US06909195B2
公开(公告)日：2005-06-21
申请号：US10826211
申请日：2004-04-16
申请人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/48
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

9. 发明申请

US20050009324A1 Trench etch process for low-k dielectrics 有权
标题翻译：低k电介质的沟槽蚀刻工艺
公开(公告)号：US20050009324A1
公开(公告)日：2005-01-13
申请号：US10826211
申请日：2004-04-16
申请人： SiYi Li , S.M. Sadjadi , David Pirkle , Stephan Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S.M. Sadjadi , David Pirkle , Stephan Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
摘要翻译：本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。优选地，该方法用于不具有中间蚀刻停止层的低k电介质。另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

10. 发明申请

US20090292628A1 SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING ITEM LEVEL TRANSACTION PROCESSING 有权
标题翻译：用于执行项目级别交易处理的系统，方法和计算机程序产品
公开(公告)号：US20090292628A1
公开(公告)日：2009-11-26
申请号：US12126707
申请日：2008-05-23
申请人： Eric Dryer , George Miller Abernethy , Ronald Hollander , Lowell Robert Huff , Sean Kang , Clarence E. Lee , Eric Scott Sandoz , Jeffrey Robert Woodside
发明人： Eric Dryer , George Miller Abernethy , Ronald Hollander , Lowell Robert Huff , Sean Kang , Clarence E. Lee , Eric Scott Sandoz , Jeffrey Robert Woodside
IPC分类号： G06Q10/00 , G06F17/30 , G06F7/06
CPC分类号： G06Q40/02 , G06Q40/12
摘要： The present invention provides systems, methods, and computer program products for performing validation and clearance at a transaction item level for transaction received in a batch format. Each transaction of the batch is stored separately in a storage system, such as a logical database. Typically, image data and electronic data for a transaction are stored separately in the storage system and may be linked to each other. Each transaction is separately accessible and/or updateable. Each transaction stored in the storage system is separately analyzed to validate that the transaction is at least balanced. Transactions that determined to be balanced are cleared irrespective of a balance status associated with other transactions associated with the batch of transactions, such that transactions are individually cleared as opposed to being cleared in a batch format.
摘要翻译：本发明提供了用于在交易项目级别执行以批量格式接收的交易的验证和清除的系统，方法和计算机程序产品。批次的每个事务分开存储在诸如逻辑数据库的存储系统中。通常，用于交易的图像数据和电子数据被分别存储在存储系统中并且可以彼此链接。每个交易可以单独访问和/或可更新。存储在存储系统中的每个事务被分开分析，以验证事务至少是平衡的。无论与批次交易相关的其他交易相关联的余额状态如何，都会清除确定为均衡的交易，这样交易将被单独清除，而不是以批量格式清除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式