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1. 发明授权

US4404736A Method for manufacturing a semiconductor device of mesa type 失效
标题翻译：台式半导体器件的制造方法
公开(公告)号：US4404736A
公开(公告)日：1983-09-20
申请号：US319411
申请日：1981-11-09
申请人： Yutaka Koshino , Takashi Ajima , Jiro Ohshima , Masahiro Abe
发明人： Yutaka Koshino , Takashi Ajima , Jiro Ohshima , Masahiro Abe
IPC分类号： H01L21/316 , H01L23/29 , H01L23/31
CPC分类号： H01L23/3171 , H01L21/316 , H01L23/291 , H01L23/3178 , H01L2924/0002 , H01L2924/3511 , Y10S148/05 , Y10S148/085 , Y10S148/159 , Y10S438/928
摘要： A method for manufacturing a semiconductor device of mesa type comprises forming mesa recesses of predetermined depth around an element in the surface of a semiconductor body, forming on the back of semiconductor body a film for lessening the concentration of stress, filling glass powder into mesa recesses, and sintering glass powder to form glass insulators. According to the method of the present invention, cracks can be prevented from being caused in the semiconductor body and glass insulators formed in mesa recesses.
摘要翻译：一种台面型半导体器件的制造方法包括在半导体本体的表面的元件周围形成预定深度的台面凹部，在半导体本体的背面形成用于减小应力集中的膜，将玻璃粉末填充到台面凹部，并烧结玻璃粉末以形成玻璃绝缘体。根据本发明的方法，可以防止在形成在台面凹部中的半导体本体和玻璃绝缘体中产生裂纹。

2. 发明授权

US4502207A Wiring material for semiconductor device and method for forming wiring pattern therewith 失效
标题翻译：用于半导体器件的接线材料及其形成布线图案的方法
公开(公告)号：US4502207A
公开(公告)日：1985-03-05
申请号：US562212
申请日：1983-12-16
申请人： Jiro Ohshima , Masahiro Abe , Yutaka Koshino
发明人： Jiro Ohshima , Masahiro Abe , Yutaka Koshino
IPC分类号： H01L21/3215 , H01L23/532 , H01L21/28
CPC分类号： H01L23/53219 , H01L21/3215 , H01L2924/0002 , Y10T428/12528
摘要： A wiring material of a semiconductor device, which comprises aluminum as a major component and at least a surface layer of the wiring layer is alloyed with boron and silicon. A method for forming a wiring material of a semiconductor device, which comprises the steps of: forming a wiring pattern comprising aluminum as a major component on a semiconductor element; and ion-implanting one of boron and a mixture of boron and silicon in the wiring pattern and alloying at least a surface layer of the wiring pattern to form an alloy layer containing aluminum, boron and silicon.
摘要翻译：包含铝作为主要成分的半导体器件的布线材料和布线层的至少表面层与硼和硅合金化。一种形成半导体器件布线材料的方法，包括以下步骤：在半导体元件上形成包含铝作为主要成分的布线图案; 并在布线图案中离子注入硼和硼与硅的混合物中的一种，并在布线图案的至少表面层合金化，形成含有铝，硼和硅的合金层。

3. 发明授权

US4415372A Method of making transistors by ion implantations, electron beam irradiation and thermal annealing 失效
标题翻译：通过离子注入，电子束照射和热退火制造晶体管的方法
公开(公告)号：US4415372A
公开(公告)日：1983-11-15
申请号：US313332
申请日：1981-10-20
申请人： Yutaka Koshino , Toshio Yonezawa , Takashi Ajima , Jiro Ohshima
发明人： Yutaka Koshino , Toshio Yonezawa , Takashi Ajima , Jiro Ohshima
IPC分类号： H01L21/263 , H01L21/265 , H01L21/324
CPC分类号： H01L21/324 , H01L21/2636 , H01L21/26513 , Y10S148/046
摘要： The invention provides a method for fabricating a semiconductor device which comprises the steps of ion-implanting an impurity into a monocrystalline semiconductor substrate; irradiating the region into which the impurity ions have been implanted with an accelerated electron beam under the conditions that the acceleration voltage is 20 to 200 KeV, and the current is 0.01 to 1 mA and the exposure dose is 10.sup.20 to 10.sup.15 /cm.sup.2 ; and carrying out annealing to form a semiconductor region of one conductivity type. According to the present invention, a semiconductor device can be fabricated which has fewer lattice defects and in which the lifetime of the carriers is long.
摘要翻译：本发明提供一种制造半导体器件的方法，该方法包括以下步骤：将杂质离子注入到单晶半导体衬底中; 在加速电压为20〜200KeV，电流为0.01〜1mA，曝光量为1020〜1015 / cm2的条件下，用加速电子束照射杂质离子注入的区域; 并进行退火以形成一种导电类型的半导体区域。根据本发明，可以制造具有更少的晶格缺陷并且其中载体的寿命长的半导体器件。

4. 发明授权

US4479830A Method of manufacturing a semiconductor device using epitaxially regrown protrusion as an alignment marker 失效
标题翻译：使用外延再生长突起作为对准标记的半导体器件的制造方法
公开(公告)号：US4479830A
公开(公告)日：1984-10-30
申请号：US462201
申请日：1983-01-31
申请人： Yutaka Koshino , Jiro Ohshima , Takashi Ajima , Toshio Yonezawa
发明人： Yutaka Koshino , Jiro Ohshima , Takashi Ajima , Toshio Yonezawa
IPC分类号： H01L21/20 , H01L21/265 , H01L23/544
CPC分类号： H01L23/544 , H01L21/2022 , H01L21/26506 , H01L21/2652 , H01L2223/54453 , H01L2924/0002
摘要： A method for manufacturing a semiconductor device is shown which includes a step of ion implanting an impurity into an impurity-region formation region of a semiconductor substrate. Before or after the ion implantation step, silicon ions are implanted in a dose of 1.times.10.sup.13 to 1.times.10.sup.15 /cm.sup.2 into the impurity-region formation region and then the silicon ions so implanted are subjected to an activation treatment to form an epitaxial grown protrusion on the surface of the substrate. The protrusion is used as an alignment mark in the subsequent mask alignment step for photolithography.
摘要翻译：示出了制造半导体器件的方法，其包括将杂质离子注入到半导体衬底的杂质区形成区域中的步骤。在离子注入步骤之前或之后，将硅离子以1×10 13至1×10 15 / cm 2的剂量注入杂质区形成区域，然后将如此注入的硅离子进行活化处理，以在表面上形成外延生长突起的基底。在随后的用于光刻的掩模对准步骤中，该突起用作对准标记。

5. 发明授权

US4515642A Method of forming deep aluminum doped silicon by implanting Al and Si ions through alumina layer and device formed thereby 失效
标题翻译：通过氧化铝层注入Al和Si离子形成深铝掺杂硅的方法和由此形成的器件
公开(公告)号：US4515642A
公开(公告)日：1985-05-07
申请号：US525484
申请日：1983-08-22
申请人： Takashi Ajima , Jiro Ohshima , Yutaka Koshino
发明人： Takashi Ajima , Jiro Ohshima , Yutaka Koshino
IPC分类号： H01L21/22 , H01L21/265 , H01L21/266 , H01L21/316
CPC分类号： H01L21/02178 , H01L21/02263 , H01L21/22 , H01L21/26506 , H01L21/2652 , H01L21/3162
摘要： In a method of producing a semiconductor device, an alumina layer is formed directly on a principal surface of a silicon substrate; aluminum and silicon are ion-implanted through the alumina layer into said substrate; and the substrate is thereafter annealed. The ion-implanted silicon yields better crystalline structure and increases the solid solubility limit of aluminum.
摘要翻译：在制造半导体器件的方法中，氧化铝层直接形成在硅衬底的主表面上; 铝和硅通过氧化铝层离子注入到所述衬底中; 然后退火基板。离子注入的硅产生更好的晶体结构并增加铝的固溶度极限。

6. 发明授权

US4780426A Method for manufacturing high-breakdown voltage semiconductor device 失效
标题翻译：高耐压半导体器件的制造方法
公开(公告)号：US4780426A
公开(公告)日：1988-10-25
申请号：US101026
申请日：1987-09-24
申请人： Yutaka Koshino , Yoshiro Baba , Jiro Ohshima
发明人： Yutaka Koshino , Yoshiro Baba , Jiro Ohshima
IPC分类号： H01L21/033 , H01L21/22 , H01L21/225 , H01L21/331 , H01L29/06 , H01L29/10 , H01L29/73 , H01L21/385 , H01L21/425
CPC分类号： H01L29/6625 , H01L21/033 , H01L21/22 , H01L21/2253 , H01L29/0615 , H01L29/1004
摘要： A first silicon oxide film is formed on the major surface of an n-type silicon substrate. A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate using the first silicon oxide film and the silicon nitride film as a mask. A second silicon oxide film is formed on the silicon substrate exposed by the opening. Gallium ions are implanted into the second silicon oxide film using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate, and the diffusion rate of gallium in the silicon oxide film is higher than that in the silicon substrate. Therefore, a p-type second layer is formed in the substrate to surround a p.sup.+ -type first layer in a self-aligned manner.
摘要翻译：在n型硅衬底的主表面上形成第一氧化硅膜。在第一氧化硅膜上形成氮化硅膜。选择性地蚀刻第一氧化硅膜和氮化硅膜以形成开口。使用第一氧化硅膜和氮化硅膜作为掩模将硼离子注入到硅衬底中。在由开口暴露的硅衬底上形成第二氧化硅膜。使用氮化硅膜作为掩模将镓离子注入到第二氧化硅膜中。硼和镓离子同时扩散到硅衬底中。在这种情况下，硅衬底中镓的扩散速率高于硅衬底中的硼的扩散速率，并且硅氧化膜中镓的扩散速率高于硅衬底中的扩散速率。因此，在衬底中形成p型第二层，以自对准的方式包围p +型第一层。

7. 发明授权

US4426234A Method of forming reproducible impurity zone of gallium or aluminum in a wafer by implanting through composite layers and diffusion annealing 失效
标题翻译：通过植入复合层和扩散退火在晶片中形成镓或铝的可再现杂质区的方法
公开(公告)号：US4426234A
公开(公告)日：1984-01-17
申请号：US327190
申请日：1981-12-03
申请人： Jiro Ohshima , Yutaka Koshino , Takashi Ajima , Toshio Yonezawa
发明人： Jiro Ohshima , Yutaka Koshino , Takashi Ajima , Toshio Yonezawa
IPC分类号： H01L21/225 , H01L21/265 , H01L21/3115 , H01L21/425 , H01L21/74
CPC分类号： H01L21/31155 , H01L21/2255 , H01L21/265
摘要： The invention discloses a method for fabricating a semiconductor device comprising the steps of: forming, on an entire surface of a semiconductor substrate of one conductivity type, a first thin film of a diffusion coefficient greater than a diffusion coefficient of the substrate; forming, on an entire surface of the first thin film, a second thin film having a diffusion coefficient smaller than the diffusion coefficient of the first thin film; ion-implanting an impurity through the second thin film into the first thin film to form an impurity region, said impurity having a conductivity type opposite to the conductivity type of the substrate; and effecting annealing to set a junction depth of the impurity region to a predetermined value. According to the method of the invention, an impurity region having a desired sheet resistivity and a desired diffusion depth can be formed in the semiconductor substrate with excellent reproducibility and control. The formation of the lattice defect can be prevented and the carrier life time can be improved. Gallium is preferably used as the impurity according to the invention.
摘要翻译：本发明公开了一种制造半导体器件的方法，包括以下步骤：在一个导电类型的半导体衬底的整个表面上形成大于衬底扩散系数的扩散系数的第一薄膜; 在所述第一薄膜的整个表面上形成扩散系数小于所述第一薄膜的扩散系数的第二薄膜; 将杂质通过第二薄膜离子注入到第一薄膜中以形成杂质区，所述杂质具有与衬底的导电类型相反的导电类型; 并进行退火以将杂质区域的结深度设定为预定值。根据本发明的方法，可以在半导体衬底中形成具有期望的电阻率和期望的扩散深度的杂质区，具有优异的再现性和控制性。可以防止晶格缺陷的形成，并且可以提高载体寿命。优选使用镓作为本发明的杂质。

8. 发明授权

US4853760A Semiconductor device having insulating layer including polyimide film 失效
标题翻译：具有包括聚酰亚胺膜的绝缘层的半导体器件
公开(公告)号：US4853760A
公开(公告)日：1989-08-01
申请号：US89959
申请日：1987-08-25
申请人： Masahiro Abe , Masaharu Aoyama , Jiro Ohshima , Takashi Ajima
发明人： Masahiro Abe , Masaharu Aoyama , Jiro Ohshima , Takashi Ajima
IPC分类号： H01L21/768 , H01L21/3105 , H01L21/3115 , H01L21/312 , H01L23/522
CPC分类号： H01L21/3105 , H01L21/31155 , H01L2924/0002
摘要： A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.
摘要翻译：半导体器件具有包括聚酰亚胺膜的钝化层。将氩离子注入到聚酰亚胺膜中以将其转化为电稳定的绝缘膜。

9. 发明授权

US4717682A Method of manufacturing a semiconductor device with conductive trench sidewalls 失效
标题翻译：制造具有导电沟槽侧壁的半导体器件的方法
公开(公告)号：US4717682A
公开(公告)日：1988-01-05
申请号：US830928
申请日：1986-02-19
申请人： Shin-ichi Taka , Jiro Ohshima , Masahiro Abe , Masaharu Aoyama
发明人： Shin-ichi Taka , Jiro Ohshima , Masahiro Abe , Masaharu Aoyama
IPC分类号： H01L21/76 , H01L21/265 , H01L21/302 , H01L21/3065 , H01L21/74 , H01L21/283
CPC分类号： H01L21/743
摘要： A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底的主表面上依次形成掩埋区域和外延层，沿着延伸到掩埋区域的环形沟槽形成导电层，用环形沟槽填充绝缘材料，并在由所述掩埋区域围绕的所述外延层中形成功能元件，并在所述环形沟槽内形成所述绝缘材料。在该方法中，沿着环形沟槽形成导电层的步骤是通过形成延伸穿过所述掩埋区域的环形沟槽以及仅在所述环形沟槽的侧壁表面上沉积导电层的步骤来执行的。

10. 发明授权

US4853342A Method of manufacturing semiconductor integrated circuit device having transistor 失效
标题翻译：具有晶体管的半导体集成电路器件的制造方法
公开(公告)号：US4853342A
公开(公告)日：1989-08-01
申请号：US300224
申请日：1989-01-24
申请人： Shin-ichi Taka , Jiro Ohshima
发明人： Shin-ichi Taka , Jiro Ohshima
IPC分类号： H01L29/73 , H01L21/20 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78
CPC分类号： H01L29/66287 , H01L21/2022 , H01L29/0826 , H01L29/1004 , H01L29/1087 , H01L29/66242 , H01L29/66651 , H01L29/732 , Y10S148/01 , Y10S148/011
摘要： A transistor is formed according to the solid phase epitaxial growth which is one of the semiconductor integrated circuit device manufacturing techniques. A low-concentration impurity region is formed by selective solid phase epitaxial growth instead of using an epitaxial substrate. The solid phase epitaxial growth is performed twice, when a collector region is formed and when a base region is formed. The depth of collector and base regions are determined by the thickness of the solid phase growth layers, respectively.
摘要翻译：根据作为半导体集成电路器件制造技术之一的固相外延生长形成晶体管。通过选择性固相外延生长而不是使用外延衬底来形成低浓度杂质区。当形成集电极区域和形成基极区域时，进行固相外延生长两次。集电极和基极区域的深度分别由固相生长层的厚度决定。

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