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1. 发明申请

US20120204141A1 Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules 有权
标题翻译：高速陶瓷模块的噪声耦合降低和阻抗不连续控制
公开(公告)号：US20120204141A1
公开(公告)日：2012-08-09
申请号：US13449732
申请日：2012-04-18
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.
摘要翻译：一种方法通过以下方式减少耦合噪声并控制陶瓷封装中的阻抗不连续性：提供至少一个参考网格层; 提供多个信号迹线层，其中每个信号层具有一个或多个信号线，并且所述参考网格层与所述信号层中的一个或多个相邻; 通过所述至少一个参考网格层布置多个通孔，其中每个通孔提供电压（Vdd）电源连接或接地（Gnd）连接; 选择性地将通过连接的共面型屏蔽（VCS）线相对于信号线放置，其中第一VCS线沿着第一信号线的第一侧延伸，并且第二VCS线沿着所述第一信号的第二相对侧延伸线。 VCS线路中的每一条与位于VCS线延伸的定向路径内的一个或多个通孔相互连接并延伸。

2. 发明授权

US08645889B2 Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules 有权
标题翻译：高速陶瓷模块中的噪声耦合减小和阻抗不连续控制
公开(公告)号：US08645889B2
公开(公告)日：2014-02-04
申请号：US13449732
申请日：2012-04-18
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： G06F17/50 , H05K1/00
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.
摘要翻译：一种方法通过以下方式减少耦合噪声并控制陶瓷封装中的阻抗不连续性：提供至少一个参考网格层; 提供多个信号迹线层，其中每个信号层具有一个或多个信号线，并且所述参考网格层与所述信号层中的一个或多个相邻; 通过所述至少一个参考网格层布置多个通孔，其中每个通孔提供电压（Vdd）电源连接或接地（Gnd）连接; 选择性地将通过连接的共面型屏蔽（VCS）线相对于信号线放置，其中第一VCS线沿着第一信号线的第一侧延伸，并且第二VCS线沿着所述第一信号的第二相对侧延伸线。 VCS线路中的每一条与位于VCS线延伸的定向路径内的一个或多个通孔相互连接并延伸。

3. 发明授权

US08288657B2 Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules 有权
标题翻译：高速陶瓷模块中的噪声耦合减小和阻抗不连续控制
公开(公告)号：US08288657B2
公开(公告)日：2012-10-16
申请号：US12577259
申请日：2009-10-12
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： H05K1/00
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.
摘要翻译：一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线第一条信号线。多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

4. 发明申请

US20110083888A1 Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules 有权
标题翻译：高速陶瓷模块的噪声耦合降低和阻抗不连续控制
公开(公告)号：US20110083888A1
公开(公告)日：2011-04-14
申请号：US12577259
申请日：2009-10-12
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： H05K1/02 , H05K3/10 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.
摘要翻译：一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线第一条信号线。多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

5. 发明授权

US08927879B2 Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures 有权
标题翻译：通过可变宽度网格平面结构在多层封装中的信号层之间的串扰降低
公开(公告)号：US08927879B2
公开(公告)日：2015-01-06
申请号：US12952152
申请日：2010-11-22
申请人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
发明人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
IPC分类号： H05K1/11 , H05K3/02 , H05K1/02
CPC分类号： H05K1/0224 , G06F17/5081 , H05K1/116 , H05K2201/09681 , H05K2201/09718 , H05K2201/09727 , Y10T29/49004 , Y10T29/49155 , Y10T29/53022
摘要： A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.
摘要翻译：网格层的网格线段的第一选择是第一宽度，并且网格层的网格线段的第二选择具有第二宽度，其中第二宽度大于第一宽度。第二宽度的网格线段的第二选择与信号层中可能引入串扰的信号线的选择平行地布置，其中遮蔽信号线选择的网线段的加宽增加了与信号相关联的返回电流将在更宽的网格线段中流动，从而增加了包含与信号相关联的电磁场的可能性，使得与其他信号的串扰减少或包含。

6. 发明申请

US20120125677A1 CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE BY VARIABLE-WIDTH MESH PLANE STRUCTURES 有权
标题翻译：可变宽度MESH PLANE结构在多层包装中的信号层之间的降噪减少
公开(公告)号：US20120125677A1
公开(公告)日：2012-05-24
申请号：US12952152
申请日：2010-11-22
申请人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
发明人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
IPC分类号： H05K1/11 , H05K3/10
CPC分类号： H05K1/0224 , G06F17/5081 , H05K1/116 , H05K2201/09681 , H05K2201/09718 , H05K2201/09727 , Y10T29/49004 , Y10T29/49155 , Y10T29/53022
摘要： A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.
摘要翻译：网格层的网格线段的第一选择是第一宽度，并且网格层的网格线段的第二选择具有第二宽度，其中第二宽度大于第一宽度。第二宽度的网格线段的第二选择与信号层中可能引入串扰的信号线的选择平行地布置，其中遮蔽信号线选择的网线段的加宽增加了与信号相关联的返回电流将在更宽的网格线段中流动，从而增加了包含与信号相关联的电磁场的可能性，使得与其他信号的串扰减少或包含。

7. 发明授权

US08276106B2 Swarm intelligence for electrical design space modeling and optimization 有权
标题翻译：用于电气设计空间建模和优化的群体智能
公开(公告)号：US08276106B2
公开(公告)日：2012-09-25
申请号：US12398535
申请日：2009-03-05
申请人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5045 , G06F2217/08
摘要： A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.
摘要翻译：一种用于探索和优化电气设计空间的方法，系统和计算机程序产品。接收设计空间的计算机分配用于优化设计空间的多个初始值（随机或预定）。产生包含多个粒子的粒子群，然后使用分配的初始值来执行设计空间的优化。在优化完成后，更新每个粒子的全球最佳和个人最好的。然后在计算机再次执行优化处理之前更新设计空间的速度向量和位置向量。过程循环，持续更新全局和个人最佳状态以及速度和位置向量，直到达到终止标准。达到终止标准后，群体的每个粒子的最佳适应度被指定为优化的设计空间。在替代实施例中，可以分配具有最差目标适应度的粒子。

8. 发明申请

US20110132650A1 High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost 有权
标题翻译：具有混合参考方案的高速陶瓷模块，用于提高性能和降低成本
公开(公告)号：US20110132650A1
公开(公告)日：2011-06-09
申请号：US12630993
申请日：2009-12-04
申请人： Wiren D. Becker , Jinwoo Choi , Tingdong Zhou
发明人： Wiren D. Becker , Jinwoo Choi , Tingdong Zhou
IPC分类号： H01R12/06 , G06F17/50 , H05K3/10
CPC分类号： H01L21/76838 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/19051 , H01L2924/3011 , H05K1/0253 , H05K3/4629 , H05K2201/09309 , H05K2201/09681 , H05K2201/09727 , H05K2201/10674 , H01L2924/00
摘要： A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.
摘要翻译：多层陶瓷封装包括：具有识别的芯片/设备区域/需要供电电源的位置的信号层; 以及设置在信号层的正上方或下方（相邻）相对侧的电压功率（Vdd）层和接地（Gnd）层，并且提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。混合网格方案包括以下不同的网格配置：在识别的芯片/设备区域之上或之下的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 并且在所有其它区域中具有更宽的网格间距，并且Vdd迹线对准以在其他区域中与信号线平行并相邻地延伸。在与信号线平行且相邻的网格区域内提供更宽的轨迹。

9. 发明授权

US07839654B2 Method for ultimate noise isolation in high-speed digital systems on packages and printed circuit boards (PCBS) 失效
标题翻译：封装和印刷电路板（PCBS）上高速数字系统中极限噪声隔离的方法
公开(公告)号：US07839654B2
公开(公告)日：2010-11-23
申请号：US11679951
申请日：2007-02-28
申请人： Jinwoo Choi
发明人： Jinwoo Choi
IPC分类号： H05K1/11
CPC分类号： H05K1/0236 , H01Q15/006 , H05K1/167 , H05K3/4641 , H05K2201/09309 , H05K2201/09681
摘要： Improved noise isolation for high-speed digital systems on packages and printed circuit boards is provided by the use of mixed alternating impedance electromagnetic bandgap (AI-EBG) structures and a power island configured to provide ultimate noise isolation. A power island is surrounded by a plurality of mixed AI-EBG structures to provide a power distribution network. In this structure, the gap around the power island provides excellent isolation from DC to the first cavity resonant frequency which is determined by the size of the structure and dielectric material. One AI-EBG structure provides excellent isolation from the first cavity resonant frequency of around 1.5 GHz to 5 GHz. The other AI-EBG structure provides excellent noise isolation from 5 GHz to 10 GHz. Through use of this novel configuration of AI-EBG structures, a combination effect of the hybrid AI-EBG structure provides excellent isolation far in excess of 10 GHz. The AI-EBG structure is a metallic-dielectric EBG structure that comprises two metal layers separated by a thin dielectric material (similar to power/ground planes in packages and PCBs). However, in the AI-EBG structure, only one of the metal layers has a periodic pattern which is preferably a two-dimensional rectangular lattice with each element consisting of a metal patch with four connecting metal branches.
摘要翻译：通过使用混合交替阻抗电磁带隙（AI-EBG）结构和配置为提供最佳噪声隔离的功率岛，提供了封装和印刷电路板上高速数字系统的改进的噪声隔离。功率岛由多个混合的AI-EBG结构包围以提供配电网络。在这种结构中，功率岛周围的间隙提供了从DC到第一腔谐振频率的良好隔离，该谐振频率由结构和介电材料的尺寸决定。一个AI-EBG结构提供了与大约1.5GHz至5GHz的第一腔共振频率的良好隔离。其他AI-EBG结构提供了从5 GHz到10 GHz的出色的噪声隔离。通过使用这种新颖的AI-EBG结构，混合AI-EBG结构的组合效果提供了超过10GHz的极好隔离。 AI-EBG结构是金属电介质EBG结构，其包括由薄的介电材料隔开的两个金属层（类似于封装和PCB中的电源/接地层）。然而，在AI-EBG结构中，只有一个金属层具有周期性图案，其优选地是二维矩形格子，每个元件由具有四个连接金属分支的金属贴片组成。

10. 发明申请

US20060092093A1 Mixed-signal systems with alternating impedance electromagnetic bandgap (AI-EBG) structures for noise suppression/isolation 有权
标题翻译：具有交流阻抗电磁带隙（AI-EBG）结构的混合信号系统，用于噪声抑制/隔离
公开(公告)号：US20060092093A1
公开(公告)日：2006-05-04
申请号：US11260952
申请日：2005-10-28
申请人： Jinwoo Choi , Madhavan Swaminathan , Vinu Govind
发明人： Jinwoo Choi , Madhavan Swaminathan , Vinu Govind
IPC分类号： H01Q15/02
CPC分类号： H01Q15/006
摘要： Alternating impedance electromagnetic bandgap (AI-EBG) structures, systems incorporating AI-EBG structures, and methods of making AI-EBG structures, are disclosed.
摘要翻译：公开了交替阻抗电磁带隙（AI-EBG）结构，包含AI-EBG结构的系统以及制造AI-EBG结构的方法。

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