专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08923053B2 Nonvolatile memory device, operating method thereof, and memory system including the same 有权
标题翻译：非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统
公开(公告)号：US08923053B2
公开(公告)日：2014-12-30
申请号：US14029100
申请日：2013-09-17
申请人： Jinman Han , Sunil Shim , Hansoo Kim , Jae-Hoon Jang , Byoungkeun Son
发明人： Jinman Han , Sunil Shim , Hansoo Kim , Jae-Hoon Jang , Byoungkeun Son
IPC分类号： G11C16/04 , G11C16/34 , H01L27/115 , G11C16/16 , G11C16/10 , H01L29/792
CPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/3418 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.
摘要翻译：提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块被单独擦除。

2. 发明授权

US08559224B2 Nonvolatile memory device, operating method thereof, and memory system including the same 有权
标题翻译：非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统
公开(公告)号：US08559224B2
公开(公告)日：2013-10-15
申请号：US13028918
申请日：2011-02-16
申请人： Jinman Han , Sunil Shim , Hansoo Kim , Jaehoon Jang , Byoungkeun Son
发明人： Jinman Han , Sunil Shim , Hansoo Kim , Jaehoon Jang , Byoungkeun Son
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/3418 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.
摘要翻译：提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块被单独擦除。

3. 发明申请

US20110199825A1 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失存储器件，其操作方法和包括其的存储器系统
公开(公告)号：US20110199825A1
公开(公告)日：2011-08-18
申请号：US13028918
申请日：2011-02-16
申请人： Jinman Han , Sunil Shim , Hansoo Kim , Jaehoon Jang , Byoungkeun Son
发明人： Jinman Han , Sunil Shim , Hansoo Kim , Jaehoon Jang , Byoungkeun Son
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/3418 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.
摘要翻译：提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块被单独擦除。

4. 发明申请

US20120322252A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY 有权
标题翻译：包含三维存储器单元阵列的半导体存储器件
公开(公告)号：US20120322252A1
公开(公告)日：2012-12-20
申请号：US13594102
申请日：2012-08-24
申请人： Byoungkeun SON , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun SON , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

5. 发明授权

US08787082B2 Semiconductor memory device comprising three-dimensional memory cell array 有权
标题翻译：包括三维存储单元阵列的半导体存储器件
公开(公告)号：US08787082B2
公开(公告)日：2014-07-22
申请号：US13594102
申请日：2012-08-24
申请人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

6. 发明授权

US08284601B2 Semiconductor memory device comprising three-dimensional memory cell array 有权
标题翻译：包括三维存储单元阵列的半导体存储器件
公开(公告)号：US08284601B2
公开(公告)日：2012-10-09
申请号：US12752485
申请日：2010-04-01
申请人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底，垂直于衬底的存储器串，存储串包括多个存储单元，以及多个细长字线，每个字线包括基本上平行于衬底的第一部分，到存储器串和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线中的第一组电连接到设置在存储器串的第一侧的第一导电线，以及第二组多个字线的组电连接到设置在存储器串的第二侧的第二导线。

7. 发明申请

US20100254191A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY 有权
标题翻译：包含三维存储器单元阵列的半导体存储器件
公开(公告)号：US20100254191A1
公开(公告)日：2010-10-07
申请号：US12752485
申请日：2010-04-01
申请人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： G11C16/02 , H01L21/3205
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 以及多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上方延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

8. 发明授权

US08908431B2 Control method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的控制方法
公开(公告)号：US08908431B2
公开(公告)日：2014-12-09
申请号：US13607038
申请日：2012-09-07
申请人： Sunil Shim , Jinman Han , Sang-Wan Nam , Won-Taeck Jung
发明人： Sunil Shim , Jinman Han , Sang-Wan Nam , Won-Taeck Jung
IPC分类号： G11C16/10 , H01L27/115 , H01L29/792 , G11C16/34 , G11C16/16
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/349 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block.
摘要翻译：根据示例性实施例，一种非易失性存储器件的控制方法，其包括在衬底上的多个存储块，每个存储块包括沿垂直于衬底的方向堆叠的多个子块，并且被配置为独立擦除，每个子块包括在垂直于衬底的方向上堆叠的多个存储单元。控制方法包括将第一存储块的计数值与参考值进行比较，所述计数值根据在第一存储器块中的数据被编程之后在第一存储器块执行的程序，读取或擦除操作的数量确定; 并且如果所述计数值大于或等于所述参考值，则执行重新编程操作，其中在第一存储器块中编程的数据被读取并且所读取的数据被编程在第二存储器块中。

9. 发明授权

US09012977B2 Semiconductor memory devices having selection transistors with nonuniform threshold voltage characteristics 有权
标题翻译：具有选择晶体管的半导体存储器件具有不均匀的阈值电压特性
公开(公告)号：US09012977B2
公开(公告)日：2015-04-21
申请号：US14154834
申请日：2014-01-14
申请人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Su-Youn Yi , Jaehoon Jang , Sunghoi Hur
发明人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Su-Youn Yi , Jaehoon Jang , Sunghoi Hur
IPC分类号： H01L29/792 , H01L29/66 , H01L27/02 , H01L27/115
CPC分类号： H01L27/0207 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.
摘要翻译：提供了一种半导体存储器件。在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

10. 发明申请

US20130313629A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20130313629A1
公开(公告)日：2013-11-28
申请号：US13830208
申请日：2013-03-14
申请人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
发明人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582
摘要： A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.
摘要翻译：一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器层，形成导电图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式