专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080233747A1 Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process 审中-公开
标题翻译：使用改进的等离子体蚀刻工艺制造的半导体器件用于完全硅化栅流程
公开(公告)号：US20080233747A1
公开(公告)日：2008-09-25
申请号：US11690198
申请日：2007-03-23
申请人： Jinhan Choi , Freidoon Mehrad , Frank S. Johnson
发明人： Jinhan Choi , Freidoon Mehrad , Frank S. Johnson
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/823835
摘要： In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch.
摘要翻译：在一个方面，我们提供了一种制造半导体器件的方法，该方法包括将氧化物层放置在栅电极和位于其附近的侧壁间隔物之间，在氧化物层上方放置保护层，进行等离子体蚀刻以去除部分保护层和第一氧化物层，其位于栅电极上方并暴露出栅电极的表面，其中等离子体蚀刻对多晶硅是选择性的。在等离子体蚀刻之后进行软蚀刻。软蚀刻包括无机基含氟气体和惰性气体，其中等离子体蚀刻在栅电极上留下一层膜，其阻止栅电极的硅化，并且其中软蚀刻去除膜。在进行软蚀刻之后，栅极用金属硅化。

2. 发明申请

US20090166629A1 REDUCING GATE CD BIAS IN CMOS PROCESSING 有权
标题翻译：降低CMOS加工中的门偏移
公开(公告)号：US20090166629A1
公开(公告)日：2009-07-02
申请号：US12241798
申请日：2008-09-30
申请人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
发明人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/82385 , H01L21/823842
摘要： A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.
摘要翻译：公开了一种形成具有NMOS晶体管和PMOS晶体管的集成电路的方法。该方法包括在半导体主体上和/或半导体本体中的NMOS区域和PMOS区域中执行预栅极处理，以及在NMOS和PMOS区域中的半导体本体上沉积多晶硅层。该方法还包括在NMOS区域和PMOS区域之一中的多晶硅层中执行第一种类型的注入，并且在NMOS和PMOS区域中的多晶硅层中进行非晶化注入，从而将多晶硅层转变为非晶硅层。该方法还包括图案化非晶硅层以形成栅电极，其中栅极位于NMOS和PMOS区两者中。

3. 发明授权

US07910422B2 Reducing gate CD bias in CMOS processing 有权
标题翻译：在CMOS处理中减少门偏置
公开(公告)号：US07910422B2
公开(公告)日：2011-03-22
申请号：US12241798
申请日：2008-09-30
申请人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
发明人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823842
摘要： A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.
摘要翻译：公开了一种形成具有NMOS晶体管和PMOS晶体管的集成电路的方法。该方法包括在半导体主体上和/或半导体本体中的NMOS区域和PMOS区域中执行预栅极处理，以及在NMOS和PMOS区域中的半导体本体上沉积多晶硅层。该方法还包括在NMOS区域和PMOS区域之一中的多晶硅层中执行第一种类型的注入，并且在NMOS和PMOS区域中的多晶硅层中进行非晶化注入，从而将多晶硅层转变为非晶硅层。该方法还包括图案化非晶硅层以形成栅电极，其中栅极位于NMOS和PMOS区两者中。

4. 发明申请

US20090104745A1 INTEGRATION METHOD FOR DUAL DOPED POLYSILICON GATE PROFILE AND CD CONTROL 审中-公开
标题翻译：双重多晶硅门型材和CD控制的集成方法
公开(公告)号：US20090104745A1
公开(公告)日：2009-04-23
申请号：US11877124
申请日：2007-10-23
申请人： Hyesook Hong , Luigi Colombo , Jinhan Choi
发明人： Hyesook Hong , Luigi Colombo , Jinhan Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/823842
摘要： In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of polysilicon gates having a first critical dimension disposed over a dielectric layer and planarizing the plurality of polysilicon gates with a spin-on material to form a plurality of planarized polysilicon gates. The method can further include doping an exposed first region with p-type dopants to form a plurality of p-doped planarized polysilicon gates and doping an exposed second region with n-type dopants to form a plurality of n-doped planarized polysilicon gates. The method can also include removing the spin-on material to form a plurality of p-doped polysilicon gates and a plurality of n-doped polysilicon gates, wherein critical dimension of each of the plurality of n-doped polysilicon gates and the plurality of p-doped polysilicon gates are substantially similar to the first critical dimension.
摘要翻译：根据本教导，提供制造双掺杂多晶硅栅极的方法。该方法可以包括提供包括多个多晶硅栅极的半导体结构，该多晶硅栅极具有设置在电介质层上的第一临界尺寸，并且用旋涂材料平坦化多个多晶硅栅极以形成多个平坦化的多晶硅栅极。该方法还可以包括用p型掺杂剂掺杂暴露的第一区域以形成多个p掺杂的平坦化多晶硅栅极，并用n型掺杂剂掺杂暴露的第二区域以形成多个n掺杂的平坦化多晶硅栅极。该方法还可以包括去除旋涂材料以形成多个p掺杂多晶硅栅极和多个n掺杂多晶硅栅极，其中多个n掺杂多晶硅栅极和多个p掺杂多晶硅栅极中的每一个的临界尺寸掺杂的多晶硅栅极基本上类似于第一临界尺寸。

5. 发明授权

US07732284B1 Post high-k dielectric/metal gate clean 有权
标题翻译：后高k电介质/金属门清洁
公开(公告)号：US07732284B1
公开(公告)日：2010-06-08
申请号：US12344421
申请日：2008-12-26
申请人： Brian K. Kirkpatrick , Jinhan Choi , Deborah J. Riley
发明人： Brian K. Kirkpatrick , Jinhan Choi , Deborah J. Riley
IPC分类号： H01L21/00
CPC分类号： H01L21/02071 , H01L21/31111 , H01L29/517 , H01L29/78 , Y10S438/906
摘要： A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.
摘要翻译：制造CMOS集成电路（IC）的方法包括提供具有半导体表面的衬底的步骤。在半导体表面上形成包括金属栅电极在包含高k电介质层的金属上的栅叠层。使用干蚀刻来图案化栅极堆叠以限定具有金属栅电极的暴露侧壁的图案化栅电极堆叠。干蚀刻形成后蚀刻残留物，其中一些沉积在基底上。包括图案化的栅极电极堆叠的衬底暴露于溶液清洁序列，其包括包括第一酸和氟化物的第一清洁步骤，用于去除至少一部分后蚀刻残留物，其中第一清洁步骤具有高选择性以避免蚀刻金属栅电极的暴露的侧壁。第一次清洁后的第二次清洁基本上由氟化物组成，其除去半导体表面上残留的高k材料。

6. 发明授权

US07754610B2 Process for etching tungsten silicide overlying polysilicon particularly in a flash memory 失效
标题翻译：用于蚀刻覆盖多晶硅的硅化钨的工艺，特别是在闪速存储器中
公开(公告)号：US07754610B2
公开(公告)日：2010-07-13
申请号：US11445709
申请日：2006-06-02
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF3和Cl2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。可以添加SiCl 4以获得额外的选择性。

7. 发明申请

US20080242072A1 PLASMA DRY ETCH PROCESS FOR METAL-CONTAINING GATES 审中-公开
标题翻译：用于含金属盖的等离子体干蚀刻工艺
公开(公告)号：US20080242072A1
公开(公告)日：2008-10-02
申请号：US11691114
申请日：2007-03-26
申请人： Jinhan Choi , Hyesook Hong , Donald S. Miles
发明人： Jinhan Choi , Hyesook Hong , Donald S. Miles
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/28079 , H01L21/28088 , H01L21/32137 , H01L29/495 , H01L29/4966
摘要： A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier layer. The method also comprises patterning the gate stack layer. Pattering includes a plasma etch of the metal nitride barrier layer. The plasma etch has a chloride-containing feed gas and a physical etch component. The physical etch component includes a high-mass species having a molecular weight of greater than about 71 gm/mol.
摘要翻译：一种制造半导体器件的方法。该方法包括形成栅堆叠层。栅堆叠在衬底上具有绝缘层，绝缘层上的含金属层，金属含有层上的金属氮化物阻挡层和金属氮化物阻挡层上的含硅层。该方法还包括图案化栅极堆叠层。溅射包括金属氮化物阻挡层的等离子体蚀刻。等离子体蚀刻具有含氯化物的进料气体和物理蚀刻部件。物理蚀刻组分包括分子量大于约71gm / mol的高质量物质。

8. 发明申请

US20070281477A1 Process for etching tungsten silicide overlying polysilicon particularly in a flash memory 失效
标题翻译：用于蚀刻覆盖多晶硅的硅化钨的工艺，特别是在闪速存储器中
公开(公告)号：US20070281477A1
公开(公告)日：2007-12-06
申请号：US11445709
申请日：2006-06-02
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank Deshmukh , Meihua Shen , Thorsten Lill , Jae Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank Deshmukh , Meihua Shen , Thorsten Lill , Jae Yu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF 3和Cl 2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。可以加入SiCl 4 4以获得额外的选择性。

9. 发明授权

US06756313B2 Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber 失效
标题翻译：在高密度等离子体室中相对于氧化物具有高选择性地蚀刻氮化硅间隔物的方法
公开(公告)号：US06756313B2
公开(公告)日：2004-06-29
申请号：US10139663
申请日：2002-05-02
申请人： Jinhan Choi , Bi Jang , Nam-hun Kim
发明人： Jinhan Choi , Bi Jang , Nam-hun Kim
IPC分类号： H01L21302
CPC分类号： H01L21/31116
摘要： We have developed a method of selectively etching silicon nitride relative to oxides in a high density plasma chamber of the kind presently known in the art. We have obtained selectivities for silicon nitride:silicon oxide in the range of about 15:1 to about 24:1. We have employed the method in the etching of silicon nitride spacers for sub 0.25 &mgr;m devices, where the spacers are adjacent to exposed oxides during the etch process. We have obtained silicon nitride spacers having rounded top corners and an extended “tail” toward the bottom outer edge of the nitride spacer. The method employs a plasma source gas which typically includes SF6, HBr, N2 and optionally, O2. Typically, the pressure in the etch chamber during etching is at least 35 mTorr and the substrate temperature is about 20° C. or less.
摘要翻译：我们开发了一种相对于现有技术中已知的高密度等离子体室中的氧化物选择性地蚀刻氮化硅的方法。我们已经获得氮化硅的选择性：氧化硅在约15:1至约24:1的范围内。我们已经采用了这种方法来蚀刻用于亚0.25微米器件的氮化硅间隔物，其中间隔物在蚀刻过程中与暴露的氧化物相邻。我们已经获得了具有圆形顶角的氮化硅间隔物和朝向氮化物间隔物的底部外边缘延伸的“尾部”。该方法采用等离子体源气体，其通常包括SF 6，HBr，N 2和任选的O 2。通常，刻蚀期间蚀刻室中的压力至少为35mTorr，衬底温度为约20℃或更低。

10. 发明申请

US20110045672A1 MULTI-FILM STACK ETCHING WITH POLYMER PASSIVATION OF AN OVERLYING ETCHED LAYER 失效
标题翻译：多层蚀刻层的聚合物钝化的多层堆叠蚀刻
公开(公告)号：US20110045672A1
公开(公告)日：2011-02-24
申请号：US12860672
申请日：2010-08-20
申请人： Sunil Srinivasan , Jinhan Choi , Anisul H. Khan
发明人： Sunil Srinivasan , Jinhan Choi , Anisul H. Khan
IPC分类号： H01L21/3065 , C23F1/08
CPC分类号： C23F4/00 , H01J37/32449 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/67069 , H01L27/0688
摘要： A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.
摘要翻译：一种用于等离子体蚀刻诸如半导体晶片的工件的方法和装置，包括具有设置在底部膜上的顶部薄膜的薄膜叠层，其间具有介于其间的中间膜。顶部和底部薄膜之间的蚀刻选择性可以低至1：1和2：1之间，并且使用第一种贫碳气体化学品来蚀刻顶部薄膜，第二种贫碳气体化学物质用于蚀刻通过使用富碳气体化学沉积顶部膜上的聚合物钝化物和用可能相同的第三种贫碳气体化学物质对底部膜进行蚀刻，交替地蚀刻中间膜和底部膜作为第一个贫碳气体化学。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式