专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070281477A1 Process for etching tungsten silicide overlying polysilicon particularly in a flash memory 失效
标题翻译：用于蚀刻覆盖多晶硅的硅化钨的工艺，特别是在闪速存储器中
公开(公告)号：US20070281477A1
公开(公告)日：2007-12-06
申请号：US11445709
申请日：2006-06-02
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank Deshmukh , Meihua Shen , Thorsten Lill , Jae Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank Deshmukh , Meihua Shen , Thorsten Lill , Jae Yu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF 3和Cl 2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。可以加入SiCl 4 4以获得额外的选择性。

2. 发明申请

US20070281479A1 Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon 审中-公开
标题翻译：包括用于蚀刻硅化钨覆盖多晶硅的硅 - 氯钝化的方法
公开(公告)号：US20070281479A1
公开(公告)日：2007-12-06
申请号：US11513455
申请日：2006-08-31
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/32137 , H01L29/40114
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 as an example of a silicon and chlorine containing passivating gas may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF 3和Cl 2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。作为含硅和氯的钝化气体的实例，可以加入作为另外选择性的SiCl 4 Si 3。

3. 发明授权

US07754610B2 Process for etching tungsten silicide overlying polysilicon particularly in a flash memory 失效
标题翻译：用于蚀刻覆盖多晶硅的硅化钨的工艺，特别是在闪速存储器中
公开(公告)号：US07754610B2
公开(公告)日：2010-07-13
申请号：US11445709
申请日：2006-06-02
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF3和Cl2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。可以添加SiCl 4以获得额外的选择性。

4. 发明授权

US06756313B2 Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber 失效
标题翻译：在高密度等离子体室中相对于氧化物具有高选择性地蚀刻氮化硅间隔物的方法
公开(公告)号：US06756313B2
公开(公告)日：2004-06-29
申请号：US10139663
申请日：2002-05-02
申请人： Jinhan Choi , Bi Jang , Nam-hun Kim
发明人： Jinhan Choi , Bi Jang , Nam-hun Kim
IPC分类号： H01L21302
CPC分类号： H01L21/31116
摘要： We have developed a method of selectively etching silicon nitride relative to oxides in a high density plasma chamber of the kind presently known in the art. We have obtained selectivities for silicon nitride:silicon oxide in the range of about 15:1 to about 24:1. We have employed the method in the etching of silicon nitride spacers for sub 0.25 &mgr;m devices, where the spacers are adjacent to exposed oxides during the etch process. We have obtained silicon nitride spacers having rounded top corners and an extended “tail” toward the bottom outer edge of the nitride spacer. The method employs a plasma source gas which typically includes SF6, HBr, N2 and optionally, O2. Typically, the pressure in the etch chamber during etching is at least 35 mTorr and the substrate temperature is about 20° C. or less.
摘要翻译：我们开发了一种相对于现有技术中已知的高密度等离子体室中的氧化物选择性地蚀刻氮化硅的方法。我们已经获得氮化硅的选择性：氧化硅在约15:1至约24:1的范围内。我们已经采用了这种方法来蚀刻用于亚0.25微米器件的氮化硅间隔物，其中间隔物在蚀刻过程中与暴露的氧化物相邻。我们已经获得了具有圆形顶角的氮化硅间隔物和朝向氮化物间隔物的底部外边缘延伸的“尾部”。该方法采用等离子体源气体，其通常包括SF 6，HBr，N 2和任选的O 2。通常，刻蚀期间蚀刻室中的压力至少为35mTorr，衬底温度为约20℃或更低。

5. 发明授权

US07910491B2 Gapfill improvement with low etch rate dielectric liners 有权
标题翻译：利用低蚀刻速率的电介质衬垫进行改进
公开(公告)号：US07910491B2
公开(公告)日：2011-03-22
申请号：US12437256
申请日：2009-05-07
申请人： Young Soo Kwon , Bi Jang , Anchuan Wang , Young S. Lee , Mihaela Balseanu , Li-Qun Xia , Jin Ho Jeon
发明人： Young Soo Kwon , Bi Jang , Anchuan Wang , Young S. Lee , Mihaela Balseanu , Li-Qun Xia , Jin Ho Jeon
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , H01L21/02112 , H01L21/02247 , H01L21/02304 , H01L21/318
摘要： A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.
摘要翻译：描述了填充沟槽的方法，并且包括在含氟蚀刻化学中沉积具有高比率的氧化硅与介电衬里蚀刻速率的介电衬垫。氧化硅沉积在沟槽内并蚀刻以重新打开或加宽沟槽顶部附近的间隙。电介质衬垫在蚀刻工艺期间保护下面的衬底，从而可以使间隙更宽。氧化硅再次沉积在沟槽内以基本上填充沟槽。

6. 发明申请

US20100099236A1 GAPFILL IMPROVEMENT WITH LOW ETCH RATE DIELECTRIC LINERS 有权
标题翻译： GAPFILL改进与低调速电介质线
公开(公告)号：US20100099236A1
公开(公告)日：2010-04-22
申请号：US12437256
申请日：2009-05-07
申请人： Young Soo Kwon , Bi Jang , Anchuan Wang , Young S. Lee , Mihaela Balseanu , Li-Qun Xia , Jin Ho Jeon
发明人： Young Soo Kwon , Bi Jang , Anchuan Wang , Young S. Lee , Mihaela Balseanu , Li-Qun Xia , Jin Ho Jeon
IPC分类号： H01L21/762 , H01L21/31
CPC分类号： H01L21/76224 , H01L21/02112 , H01L21/02247 , H01L21/02304 , H01L21/318
摘要： A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.
摘要翻译：描述了填充沟槽的方法，并且包括在含氟蚀刻化学中沉积具有高比率的氧化硅与介电衬里蚀刻速率的介电衬垫。氧化硅沉积在沟槽内并蚀刻以重新打开或加宽沟槽顶部附近的间隙。电介质衬垫在蚀刻工艺期间保护下面的衬底，从而可以使间隙更宽。氧化硅再次沉积在沟槽内以基本上填充沟槽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式