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1. 发明申请

US20090166629A1 REDUCING GATE CD BIAS IN CMOS PROCESSING 有权
标题翻译：降低CMOS加工中的门偏移
公开(公告)号：US20090166629A1
公开(公告)日：2009-07-02
申请号：US12241798
申请日：2008-09-30
申请人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
发明人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/82385 , H01L21/823842
摘要： A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.
摘要翻译：公开了一种形成具有NMOS晶体管和PMOS晶体管的集成电路的方法。该方法包括在半导体主体上和/或半导体本体中的NMOS区域和PMOS区域中执行预栅极处理，以及在NMOS和PMOS区域中的半导体本体上沉积多晶硅层。该方法还包括在NMOS区域和PMOS区域之一中的多晶硅层中执行第一种类型的注入，并且在NMOS和PMOS区域中的多晶硅层中进行非晶化注入，从而将多晶硅层转变为非晶硅层。该方法还包括图案化非晶硅层以形成栅电极，其中栅极位于NMOS和PMOS区两者中。

2. 发明授权

US07910422B2 Reducing gate CD bias in CMOS processing 有权
标题翻译：在CMOS处理中减少门偏置
公开(公告)号：US07910422B2
公开(公告)日：2011-03-22
申请号：US12241798
申请日：2008-09-30
申请人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
发明人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823842
摘要： A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.
摘要翻译：公开了一种形成具有NMOS晶体管和PMOS晶体管的集成电路的方法。该方法包括在半导体主体上和/或半导体本体中的NMOS区域和PMOS区域中执行预栅极处理，以及在NMOS和PMOS区域中的半导体本体上沉积多晶硅层。该方法还包括在NMOS区域和PMOS区域之一中的多晶硅层中执行第一种类型的注入，并且在NMOS和PMOS区域中的多晶硅层中进行非晶化注入，从而将多晶硅层转变为非晶硅层。该方法还包括图案化非晶硅层以形成栅电极，其中栅极位于NMOS和PMOS区两者中。

3. 发明申请

US20080268631A1 Method of Forming a Silicided Gate Utilizing a CMP Stack 有权
标题翻译：使用CMP堆叠形成硅化浇口的方法
公开(公告)号：US20080268631A1
公开(公告)日：2008-10-30
申请号：US11741064
申请日：2007-04-27
申请人： Frank Scott Johnson , Freidoon Mehrad
发明人： Frank Scott Johnson , Freidoon Mehrad
IPC分类号： H01L21/8238 , H01L21/311
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate.
摘要翻译：一种用于制造半导体器件的方法包括利用CMP叠层形成硅化栅。 CMP堆叠包括形成在下面的半导体器件上的第一衬垫和形成在第一衬里层上的第一介电层。第一电介质层形成为大约高度的栅极。在第一介电层上形成第二衬里层。由于第一电介质层形成为大致高度的栅极，护套区域上的第二衬垫大约在栅极上的第一衬垫的高度处。执行CMP处理以在栅极的顶部上露出第一衬垫。由于第一电介质层形成到栅极的高度，所以在CMP工艺之后，第二衬里的一部分保留在护环区域之上。之后，露出栅极，进行硅化处理以形成硅化栅极。

4. 发明申请

US20080206973A1 Process method to optimize fully silicided gate (FUSI) thru PAI implant 审中-公开
标题翻译：通过PAI植入物优化完全硅化栅（FUSI）的工艺方法
公开(公告)号：US20080206973A1
公开(公告)日：2008-08-28
申请号：US11710769
申请日：2007-02-26
申请人： Frank Scott Johnson , Freidoon Mehrad , Jiong-Ping Lu
发明人： Frank Scott Johnson , Freidoon Mehrad , Jiong-Ping Lu
IPC分类号： H01L21/3205
CPC分类号： H01L21/26506 , H01L21/28097 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a blocking layer over the etch-stop layer, planarizing the blocking layer down to the etch-stop layer over the gates, and removing a portion of the etch-stop layer overlying the gates. The method further includes implanting a preamorphizing species into the exposed gates to amorphize the gates, thereby permitting uniform silicide formation thereafter at substantially the same rates in the NMOS and PMOS transistors. The method may further comprise removing any remaining oxide or blocking layers, forming the gate silicide over the gates to form the FUSI gates, and forming source/drain silicide in moat areas of the NMOS and PMOS transistors.
摘要翻译：公开了在相同MOS器件的NMOS和PMOS晶体管中形成完全硅化（FUSI）栅极的改进方法。在一个示例中，该方法包括在NMOS和PMOS晶体管的栅极的顶部部分上形成氧化物和氮化物蚀刻停止层，在蚀刻停止层上形成阻挡层，将阻挡层平坦化到蚀刻停止并且去除覆盖在栅极上的蚀刻停止层的一部分。该方法还包括将预变质物质注入到暴露的栅极中以使栅极非晶化，从而在NMOS和PMOS晶体管中以基本上相同的速率允许均匀的硅化物形成。该方法还可以包括去除任何剩余的氧化物或阻挡层，在栅极上形成栅极硅化物以形成FUSI栅极，以及在NMOS和PMOS晶体管的护环区域中形成源极/漏极硅化物。

5. 发明授权

US07763540B2 Method of forming a silicided gate utilizing a CMP stack 有权
标题翻译：使用CMP堆叠形成硅化栅的方法
公开(公告)号：US07763540B2
公开(公告)日：2010-07-27
申请号：US11741064
申请日：2007-04-27
申请人： Frank Scott Johnson , Freidoon Mehrad
发明人： Frank Scott Johnson , Freidoon Mehrad
IPC分类号： H01L21/44
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate.
摘要翻译：一种用于制造半导体器件的方法包括利用CMP叠层形成硅化栅。 CMP堆叠包括形成在下面的半导体器件上的第一衬垫和形成在第一衬里层上的第一介电层。第一电介质层形成为大约高度的栅极。在第一介电层上形成第二衬里层。由于第一电介质层形成为大致高度的栅极，护套区域上的第二衬垫大约在栅极上的第一衬垫的高度处。执行CMP处理以在栅极的顶部上露出第一衬垫。由于第一电介质层形成到栅极的高度，所以在CMP工艺之后，第二衬里的一部分保留在护环区域之上。之后，露出栅极，进行硅化处理以形成硅化栅极。

6. 发明授权

US07960287B2 Methods for fabricating FinFET structures having different channel lengths 有权
标题翻译：制造具有不同沟道长度的FinFET结构的方法
公开(公告)号：US07960287B2
公开(公告)日：2011-06-14
申请号：US12891365
申请日：2010-09-27
申请人： Frank Scott Johnson , Richard T. Schultz
发明人： Frank Scott Johnson , Richard T. Schultz
IPC分类号： H01L21/311
CPC分类号： H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.
摘要翻译：提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

7. 发明申请

US20090286375A1 METHOD OF FORMING SIDEWALL SPACERS TO REDUCE FORMATION OF RECESSES IN THE SUBSTRATE AND INCREASE DOPANT RETENTION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：形成侧壁间隔的方法，以减少在基底中形成的凹陷并增加半导体器件中的氘保持
公开(公告)号：US20090286375A1
公开(公告)日：2009-11-19
申请号：US12122885
申请日：2008-05-19
申请人： Mahalingam Nandakumar , Said Ghneim , Frank Scott Johnson
发明人： Mahalingam Nandakumar , Said Ghneim , Frank Scott Johnson
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L29/6656
摘要： A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer.
摘要翻译：在半导体器件中形成用于栅极的侧壁间隔物的方法包括：在栅极形成之后，再次氧化/退火衬底的硅和栅极的硅。通过在惰性气氛或环境中进行退火，使基板再次氧化。在沉积覆盖衬底和栅极的氧化物层之后，衬底可以被再氧化/退火。此外，可以在形成栅极之后再次氧化/退火衬底，而不沉积氧化物层。

8. 发明申请

US20090125865A1 SYSTEM AND METHOD FOR MAKING PHOTOMASKS 有权
标题翻译：制作光子的系统和方法
公开(公告)号：US20090125865A1
公开(公告)日：2009-05-14
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50 , H05K1/00
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

9. 发明授权

US08729609B2 Integrated circuits including multi-gate transistors locally interconnected by continuous fin structure and methods for the fabrication thereof 有权
标题翻译：集成电路包括通过连续鳍结构局部互连的多栅极晶体及其制造方法
公开(公告)号：US08729609B2
公开(公告)日：2014-05-20
申请号：US12711022
申请日：2010-02-23
申请人： Frank Scott Johnson , Andreas Knorr
发明人： Frank Scott Johnson , Andreas Knorr
IPC分类号： H01L29/66
CPC分类号： H01L27/1207 , H01L21/76895 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.
摘要翻译：提供集成电路的实施例。在一个实施例中，集成电路包括衬底和多个局部互连的多栅极晶体管。多个本地互连的多栅极晶体管包括形成在衬底上的连续鳍结构，以及形成在衬底上的第一和第二多栅极晶体管，并且分别包括连续鳍结构的第一鳍片段和第二鳍片段。连续翅片结构使第一和第二多栅极晶体管电连接。

10. 发明申请

US20130309838A1 METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES 有权
标题翻译：在半导体衬底上制造FINFET集成电路的方法
公开(公告)号：US20130309838A1
公开(公告)日：2013-11-21
申请号：US13474443
申请日：2012-05-17
申请人： Andy C. Wei , Francis C. Tambwe , Frank Scott Johnson
发明人： Andy C. Wei , Francis C. Tambwe , Frank Scott Johnson
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/3086 , H01L21/823821 , H01L29/6681
摘要： Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.
摘要翻译：提供了用于在体半导体衬底上制造FinFET集成电路的方法。根据一个实施例，形成覆盖半导体衬底的限定多个翅片的规则阵列的位置的图案化硬掩模。使用切割掩模去除图案化硬掩模的部分以形成修改的硬掩模。使用改进的硬掩模作为蚀刻掩模蚀刻衬底，以形成从衬底向上延伸并由沟槽分离的多个鳍。至少部分地去除多个翅片中的选定的翅片以形成隔离区域，并且沉积绝缘材料以填充沟槽并且覆盖多个翅片中的至少部分移除的选定翼片。

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