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1. 发明授权

US07208065B2 Structure for measuring the etching speed 有权
标题翻译：用于测量蚀刻速度的结构
公开(公告)号：US07208065B2
公开(公告)日：2007-04-24
申请号：US10875306
申请日：2004-06-25
申请人： Jing-Hung Chiou , Kai-Hsiang Yen , Chin-Horng Wang , Chao-Chiun Liang , Stella Y. H. Chen
发明人： Jing-Hung Chiou , Kai-Hsiang Yen , Chin-Horng Wang , Chao-Chiun Liang , Stella Y. H. Chen
IPC分类号： H01L21/306
CPC分类号： B81C99/004 , H01L22/34
摘要： The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.
摘要翻译：该说明书公开了一种用于测量蚀刻速度的结构和方法。测试层与几个电阻相连。金属层的蚀刻使电阻与电路顺序断开。测量感测电阻器系统的等效电阻以获得蚀刻速度。考虑到电阻器的误差，本发明还提供一种利用IC布局技术将交错式虚拟电阻器放置在感测电阻器旁边的结构。通过获取感测电阻器和虚拟电阻器的等效电阻的比率，本发明可以计算以获得蚀刻速度。

2. 发明授权

US06828164B2 Method for measuring the etching speed 失效
标题翻译：测量蚀刻速度的方法
公开(公告)号：US06828164B2
公开(公告)日：2004-12-07
申请号：US10402995
申请日：2003-04-01
申请人： Jing-Hung Chiou , Kai-Hsiang Yen , Chin-Horng Wang , Chao-Chiun Liang , Stella Y. H. Chen
发明人： Jing-Hung Chiou , Kai-Hsiang Yen , Chin-Horng Wang , Chao-Chiun Liang , Stella Y. H. Chen
IPC分类号： H01L2166
CPC分类号： B81C99/004 , H01L22/34
摘要： The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.
摘要翻译：该说明书公开了一种用于测量蚀刻速度的结构和方法。测试层与几个电阻相连。金属层的蚀刻使电阻与电路顺序断开。测量感测电阻器系统的等效电阻以获得蚀刻速度。考虑到电阻器的误差，本发明还提供一种利用IC布局技术将交错式虚拟电阻器放置在感测电阻器旁边的结构。通过获取感测电阻器和虚拟电阻器的等效电阻的比率，本发明可以计算以获得蚀刻速度。

3. 发明申请

US20060001114A1 Apparatus and method of wafer level package 审中-公开
标题翻译：晶圆级封装的装置和方法
公开(公告)号：US20060001114A1
公开(公告)日：2006-01-05
申请号：US10927066
申请日：2004-08-27
申请人： Jen-Yi Chen , Jing-Hung Chiou , Kai-Hsiang Yen
发明人： Jen-Yi Chen , Jing-Hung Chiou , Kai-Hsiang Yen
IPC分类号： H01L29/82
CPC分类号： B81C1/00301 , B81B2207/095 , B81C1/00896 , B81C2201/053 , H01L21/50 , H01L23/04 , H01L23/055 , H01L23/24 , H01L2224/05001 , H01L2224/05022 , H01L2224/16 , H01L2924/00014 , H01L2924/16235 , H01L2224/05599 , H01L2224/05099
摘要： An apparatus of wafer level package for the micro elements and methods of fabricating the same is disclosed. The apparatus is utilized to provide a lid substrate for bonding the lid substrate to a substrate having several micro elements and therefore form a cavity capable of being operated for the micro elements. The openings of the cavity are used to make the micro elements capable of being contacted with the atmosphere and therefore form an apparatus of wafer level package for the micro elements.
摘要翻译：公开了一种用于微元件的晶片级封装的装置及其制造方法。该装置用于提供用于将盖基板接合到具有几个微元件的基板的盖基板，因此形成能够对微元件进行操作的空腔。空腔的开口用于使微元件能够与大气接触，并且因此形成用于微元件的晶片级封装的装置。

4. 发明授权

US06600644B1 Microelectronic tunable capacitor and method for fabrication 有权
标题翻译：微电子可调电容器及其制造方法
公开(公告)号：US06600644B1
公开(公告)日：2003-07-29
申请号：US10233905
申请日：2002-09-03
申请人： Jing-Hung Chiou , Kai-Hsiang Yen , Ran-Jin Lin , Jia-Hroung Wu , Kun-Ho Chou
发明人： Jing-Hung Chiou , Kai-Hsiang Yen , Ran-Jin Lin , Jia-Hroung Wu , Kun-Ho Chou
IPC分类号： H01G504
CPC分类号： H01G5/04
摘要： A microelectronic tunable capacitor and a method for fabricating the capacitor are described. The capacitor is formed by a micro-actuator, a first fixed capacitor plate and a second swayable capacitor plate suspended over the first plate. The micro-actuator is formed by a pair of fixed electrodes positioned spaced-apart from each other sandwiching without contact a suspended arm electrode swayable between the pair of fixed eletrodes. The second swayable capacitor plate is mounted to the suspended arm and sways by an electrostatic force between the pair of fixed electrodes to suitably adjust a desirable capacitance for the tunable capacitor.
摘要翻译：描述了微电子可调谐电容器和制造电容器的方法。电容器由微致动器，第一固定电容器板和悬挂在第一板上的第二摇摆电容器板形成。微型致动器由一对固定电极形成，该对电极彼此间隔开夹住而不接触可摆动在一对固定电极之间的悬臂臂电极。第二摇摆式电容器板通过一对固定电极之间的静电力安装到悬臂上并适当调节可调谐电容器所需的电容。

5. 发明授权

US07125795B2 Fabrication method for microstructures with high aspect ratios 有权
标题翻译：具有高纵横比的微结构的制造方法
公开(公告)号：US07125795B2
公开(公告)日：2006-10-24
申请号：US10992709
申请日：2004-11-22
申请人： Nai-Hao Kuo , Kai-Hsiang Yen , Jing-Hung Chiou , Po-Hao Tsai , Yuh-Wen Lee
发明人： Nai-Hao Kuo , Kai-Hsiang Yen , Jing-Hung Chiou , Po-Hao Tsai , Yuh-Wen Lee
IPC分类号： H01L21/4763
CPC分类号： B81C1/00619 , G01P15/0802
摘要： A fabrication method for microstructures with high aspect ratios uses a CMOS process to form a desired microstructure on a silicon substrate. The steps of forming a contact plug and a via plug of the process are used to form etching channels in insulation layers, polysilicon layers and metal layers, penetrating to the silicon substrate. An etching process is then performed through the etching channel to form the desired microstructure with high aspect ratio.
摘要翻译：具有高纵横比的微结构的制造方法使用CMOS工艺在硅衬底上形成期望的微结构。形成该工艺的接触塞和通孔的步骤用于在绝缘层，多晶硅层和金属层中形成穿透到硅衬底的蚀刻通道。然后通过蚀刻通道进行蚀刻工艺以形成具有高纵横比的所需微结构。

6. 发明申请

US20050064650A1 Fabrication method for microstructures with high aspect ratios 有权
标题翻译：具有高纵横比的微结构的制造方法
公开(公告)号：US20050064650A1
公开(公告)日：2005-03-24
申请号：US10992709
申请日：2004-11-22
申请人： Nai-Hao Kuo , Kai-Hsiang Yen , Jing-Hung Chiou , Po-Hao Tsai , Yuh-Wen Lee
发明人： Nai-Hao Kuo , Kai-Hsiang Yen , Jing-Hung Chiou , Po-Hao Tsai , Yuh-Wen Lee
IPC分类号： B81C99/00 , G01P15/08 , H01L21/8238
CPC分类号： B81C1/00619 , G01P15/0802
摘要： A fabrication method for microstructures with high aspect ratios uses a CMOS process to form a desired microstructure on a silicon substrate. The steps of forming a contact plug and a via plug of the process are used to form etching channels in insulation layers, polysilicon layers and metal layers, penetrating to the silicon substrate. An etching process is then performed through the etching channel to form the desired microstructure with high aspect ratio.
摘要翻译：具有高纵横比的微结构的制造方法使用CMOS工艺在硅衬底上形成期望的微结构。形成该工艺的接触塞和通孔的步骤用于在绝缘层，多晶硅层和金属层中形成穿透到硅衬底的蚀刻通道。然后通过蚀刻通道进行蚀刻工艺以形成具有高纵横比的所需微结构。

7. 发明授权

US06804443B2 Test structure and method of step coverage for optical waveguide production 有权
标题翻译：光波导生产阶梯覆盖的测试结构和方法
公开(公告)号：US06804443B2
公开(公告)日：2004-10-12
申请号：US10601647
申请日：2003-06-24
申请人： Po-Hao Tsai , Jing-Hung Chiou , Kai-Hsiang Yen , Wen-Jiun Liu , Yuh-Wen Lee
发明人： Po-Hao Tsai , Jing-Hung Chiou , Kai-Hsiang Yen , Wen-Jiun Liu , Yuh-Wen Lee
IPC分类号： G02B610
CPC分类号： G02B6/132 , G02B2006/12176
摘要： Test structure and method of step coverage for optical waveguide production are disclosed. It combines the steps of producing the optical waveguide and the testing structure by forming the optical waveguide components on the chip and the test structure in the surrounding areas, so the optical waveguide and the test structure have the same upper covering layer. Etching solution is used for the etch testing of the test structure, and the step coverage of the upper covering layer for the optical waveguide is extrapolated by the etching result.
摘要翻译：公开了用于光波导生产的步骤覆盖的测试结构和方法。它结合了通过在芯片上形成光波导部件和周围区域的测试结构来生产光波导和测试结构的步骤，因此光波导和测试结构具有相同的上覆盖层。蚀刻溶液用于测试结构的蚀刻测试，并且通过蚀刻结果外推了用于光波导的上覆盖层的台阶覆盖。

8. 发明授权

US08508022B2 Ultra thin package for electric acoustic sensor chip of micro electro mechanical system 有权
标题翻译：微电子机械系统电声传感器芯片超薄封装
公开(公告)号：US08508022B2
公开(公告)日：2013-08-13
申请号：US12172900
申请日：2008-07-14
申请人： Tzong-Che Ho , Jason Pan , Pin Chang , Chin-Horng Wang , Jung-Tai Chen , Hsin-Li Lee , Kai-Hsiang Yen
发明人： Tzong-Che Ho , Jason Pan , Pin Chang , Chin-Horng Wang , Jung-Tai Chen , Hsin-Li Lee , Kai-Hsiang Yen
IPC分类号： H01L23/552 , H01L21/00 , H05K7/00
CPC分类号： H04R19/005 , B81B7/0058 , B81B2201/0257 , H01L2924/0002 , H01L2924/00
摘要： An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed.
摘要翻译：提供了一种用于微机电系统的电声传感器芯片的超薄封装。衬底具有与第一衬底表面相对的第一衬底表面和第二衬底表面。在第二基板表面上形成至少一个导体凸块。提供具有与第一芯片表面相对的第一芯片表面和第二芯片表面的电声传感器芯片。第一芯片表面电连接到导体凸块。导体凸块位于第二基板表面和第一芯片表面之间以产生空间。导体凸块用于将信号从传感器芯片传送到基板。形成通过基板的声学开口。

9. 发明申请

US20090161901A1 ULTRA THIN PACKAGE FOR ELECTRIC ACOUSTIC SENSOR CHIP OF MICRO ELECTRO MECHANICAL SYSTEM 有权
标题翻译：微电子机械系统电声传感器芯片超薄包
公开(公告)号：US20090161901A1
公开(公告)日：2009-06-25
申请号：US12172900
申请日：2008-07-14
申请人： Tzong-Che Ho , Jason Pan , Pin Chang , Chin-Horng Wang , Jung-Tai Chen , Hsin-Li Lee , Kai-Hsiang Yen
发明人： Tzong-Che Ho , Jason Pan , Pin Chang , Chin-Horng Wang , Jung-Tai Chen , Hsin-Li Lee , Kai-Hsiang Yen
IPC分类号： H04R1/00
CPC分类号： H04R19/005 , B81B7/0058 , B81B2201/0257 , H01L2924/0002 , H01L2924/00
摘要： An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed.
摘要翻译：提供了一种用于微机电系统的电声传感器芯片的超薄封装。衬底具有与第一衬底表面相对的第一衬底表面和第二衬底表面。在第二基板表面上形成至少一个导体凸块。提供具有与第一芯片表面相对的第一芯片表面和第二芯片表面的电声传感器芯片。第一芯片表面电连接到导体凸块。导体凸块位于第二基板表面和第一芯片表面之间以产生空间。导体凸块用于将信号从传感器芯片传送到基板。形成通过基板的声学开口。

10. 发明授权

US08039910B2 Electro-acoustic sensing device 有权
标题翻译：电声传感装置
公开(公告)号：US08039910B2
公开(公告)日：2011-10-18
申请号：US11964995
申请日：2007-12-27
申请人： Kai-Hsiang Yen , Jen-Yi Chen , Po-Hsun Sung
发明人： Kai-Hsiang Yen , Jen-Yi Chen , Po-Hsun Sung
IPC分类号： H01L29/84
CPC分类号： B81C1/0023 , B81B2201/0257 , B81B2207/012 , H01L2224/48091 , H01L2224/48137 , H01L2924/10253 , H01L2924/1461 , H01L2924/3025 , H04R19/005 , H04R31/00 , H01L2924/00014 , H01L2924/00
摘要： An electro-acoustic sensing device including a sensing chip, a carrier chip and a sealing element is provided. The sensing chip is for electro-acoustic transuding and thereby outputting an electrical signal. The carrier chip disposed below the sensing chip has at least one second connecting point, at least one electrical channel and at least one channel connecting point. The second connecting point is electrically contacted with the first connecting point. The second connecting point and the channel connecting point are located at different surfaces of the carrier chip. The electrical channel passes through the carrier chip and electrically connects the second connecting point and the channel connecting point. The electrical signal is transmitted to the channel connecting point via the first and the second connecting points and the electrical channel. The sealing element is disposed between the sensing chip and the carrier chip for air-tight coupling the two chips.
摘要翻译：提供了包括感测芯片，载体芯片和密封元件的电声感测装置。感测芯片用于电声输出，从而输出电信号。布置在感测芯片下方的载体芯片具有至少一个第二连接点，至少一个电通道和至少一个通道连接点。第二连接点与第一连接点电接触。第二连接点和通道连接点位于载体芯片的不同表面。电气通道穿过载体芯片并电连接第二连接点和通道连接点。电信号通过第一和第二连接点和电通道传输到通道连接点。密封元件设置在感测芯片和载体芯片之间，用于气密地耦合两个芯片。

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