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1. 发明授权

US07724574B2 Semiconductor memory device and data write and read method thereof 有权
标题翻译：半导体存储器件及其数据写入和读取方法
公开(公告)号：US07724574B2
公开(公告)日：2010-05-25
申请号：US11769758
申请日：2007-06-28
申请人： Jin-Kuk Kim , Woo-Seop Jeong
发明人： Jin-Kuk Kim , Woo-Seop Jeong
IPC分类号： G11C16/04
CPC分类号： G11C29/26 , G11C2029/1202 , G11C2029/1802 , G11C2029/2602
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.
摘要翻译：一种半导体存储器件包括：存储单元阵列，包括多个存储体;地址输入部分，其在正常模式操作期间通过地址引脚接收行地址和列地址，并接收行地址，列地址和写入数据在测试模式操作期间通过地址引脚，响应于行地址和测试模式操作期间在测试模式操作期间访问在正常模式操作期间多个存储体之一中的一个存储器组中的至少两个存储器组的地址译码器列地址，数据输入部分，其在正常模式操作期间将通过数据引脚施加的写数据输入到存储单元阵列，并且在测试模式操作期间将从地址输入部分输出的写数据输入到存储单元阵列;以及数据输出部分，其在正常模式操作和测试模式操作期间将从存储单元阵列输出的读取数据输出到数据引脚离子。

2. 发明申请

US20080094890A1 SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE AND READ METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据写入及其读取方法
公开(公告)号：US20080094890A1
公开(公告)日：2008-04-24
申请号：US11769758
申请日：2007-06-28
申请人： Jin-Kuk Kim , Woo-Seop Jeong
发明人： Jin-Kuk Kim , Woo-Seop Jeong
IPC分类号： G11C16/06
CPC分类号： G11C29/26 , G11C2029/1202 , G11C2029/1802 , G11C2029/2602
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.
摘要翻译：一种半导体存储器件包括：存储单元阵列，包括多个存储体;地址输入部分，其在正常模式操作期间通过地址引脚接收行地址和列地址，并接收行地址，列地址和写入数据在测试模式操作期间通过地址引脚，响应于行地址和测试模式操作期间在测试模式操作期间访问在正常模式操作期间多个存储体之一中的一个存储器组中的至少两个存储器组的地址译码器列地址，数据输入部分，其在正常模式操作期间将通过数据引脚施加的写数据输入到存储单元阵列，并且在测试模式操作期间将从地址输入部分输出的写数据输入到存储单元阵列;以及数据输出部分，其在正常模式操作和测试模式操作期间将从存储单元阵列输出的读取数据输出到数据引脚离子。

3. 发明授权

US07782688B2 Semiconductor memory device and test method thereof 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US07782688B2
公开(公告)日：2010-08-24
申请号：US12004715
申请日：2007-12-21
申请人： Yong-Jun Kim , Woo-Seop Jeong , Kyu-Chan Lee
发明人： Yong-Jun Kim , Woo-Seop Jeong , Kyu-Chan Lee
IPC分类号： G11C7/00
CPC分类号： G11C29/56 , G01R31/318511 , G11C29/006 , G11C29/1201 , G11C29/48 , G11C2029/5602 , H01L2224/06156
摘要： Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.
摘要翻译：提供半导体存储器件及其测试方法。半导体存储器件包括：集成有多个内部电路的管芯; 具有第一焊盘尺寸和第一焊盘间距的多个第一和第二通道焊盘，以交替的方式设置在模具的中心部分处的直线上，并且被分成多个平行的行，其中多个第一焊盘并且第二通道焊盘被配置为以交替方式选择性地接触测试探针以接收外部晶片测试信号并将由多个内部电路产生的信号输出到外部。因此，可以在半导体存储器件的晶片测试期间使用多个探针卡的探针来进行使用多个通道焊盘的测试，而不会与相邻的焊盘不接触或不接触。

4. 发明申请

US20120106283A1 Row Address Control Circuit Semiconductor Memory Device Including The Same And Method Of Controlling Row Address 失效
标题翻译：行地址控制电路包括相同的半导体存储器件和控制行地址的方法
公开(公告)号：US20120106283A1
公开(公告)日：2012-05-03
申请号：US13237353
申请日：2011-09-20
申请人： Hui-Kap Yang , Woo-Seop Jeong , Chul-Sung Park
发明人： Hui-Kap Yang , Woo-Seop Jeong , Chul-Sung Park
IPC分类号： G11C11/402 , G11C8/00 , G11C8/04
CPC分类号： G11C29/20 , G11C2029/1802
摘要： A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.
摘要翻译：包括动态存储单元的半导体存储器件的行地址控制电路包括测试模式设置单元，地址计数器和行地址生成单元。测试模式设置单元被配置为响应于测试命令提供指示是否执行测试操作的测试模式信号; 地址计数器被配置为生成逐渐增加的第一地址; 并且行地址生成单元被配置为基于测试模式信号选择性地选择第一地址和第二地址中的一个作为刷新地址，第二地址被外部提供。

5. 发明申请

US20080157076A1 Semiconductor device with test pads and pad connection unit 有权
标题翻译：具有测试焊盘和焊盘连接单元的半导体器件
公开(公告)号：US20080157076A1
公开(公告)日：2008-07-03
申请号：US12004401
申请日：2007-12-20
申请人： Woo-Seop Jeong
发明人： Woo-Seop Jeong
IPC分类号： H01L23/58
CPC分类号： G11C29/1201 , G01R31/2884 , G11C29/48 , H01L22/32 , H01L2224/05554 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.
摘要翻译：半导体器件包括至少一种第一类型的焊盘和至少一种第二类型的焊盘，其具有与第一类型焊盘不同的区域。焊盘连接单元在测试模式期间将所述至少一个第二类型的焊盘电耦合到所述半导体器件的集成电路，并且在正常操作模式期间将所述至少一个第二类型的焊盘与所述集成电路断开。

6. 发明授权

US07336558B2 Semiconductor memory device with reduced number of pads 有权
标题翻译：具有减少焊盘数量的半导体存储器件
公开(公告)号：US07336558B2
公开(公告)日：2008-02-26
申请号：US11264512
申请日：2005-10-31
申请人： Woo-Seop Jeong
发明人： Woo-Seop Jeong
IPC分类号： G11C8/00
CPC分类号： G11C29/1201 , G11C5/066 , G11C29/48
摘要： A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the external clock signal.
摘要翻译：提供了一种半导体存储器件，其包括一组地址焊盘和一个输入电路，该输入电路被配置为在外部时钟信号的第一转变处接收来自地址焊盘的第一地址，并且在第二转换时从地址焊盘接收第二地址外部时钟信号。

7. 发明授权

US6151270A Integrated circuit memory devices having programmable latency periods and methods of operating same 有权
标题翻译：具有可编程延迟周期的集成电路存储器件及其操作方法
公开(公告)号：US6151270A
公开(公告)日：2000-11-21
申请号：US134586
申请日：1998-08-14
申请人： Woo-Seop Jeong
发明人： Woo-Seop Jeong
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： Integrated circuit memory devices include a column select signal generator which generates a column select signal (CSL) having leading and trailing edges and a preferred timing controller. The timing controller, which is electrically coupled to the column select signal generator and is responsive to at least one latency state signal (e.g., CLy), adjusts the timing of at least one of the leading and trailing edges of the column select signal pulse as a function of the value of the at least one latency state signal. Here, the value of the latency state signal can be adjusted to cause a shift in the timing of the column select signal (CSL) and thereby reduce the likelihood of reading errors. In particular, the timing controller is responsive to a first internal clock signal (e.g., PCLK) and generates first and second control signals as CSLE and CSLD. The column select signal generator is responsive to the first and second control signals. The first control signal is preferably delayed and inverted relative to the first internal clock signal by a first delay and the second control signal is preferably delayed relative to the first internal clock signal by a second delay which is less than the first delay. The timing controller also adjusts the timing of at least one of the leading and trailing edges of the column select signal by adjusting the values of the first and second delays as a function of the value of the at least one latency state signal.
摘要翻译：集成电路存储器件包括产生具有前沿和后沿的列选择信号（CSL）的列选择信号发生器和优选的时序控制器。电气耦合到列选择信号发生器并且响应于至少一个等待时间状态信号（例如，CLy）的定时控制器将列选择信号脉冲的前沿和后沿中的至少一个的定时调整为是至少一个等待时间状态信号的值的函数。这里，等待状态信号的值可以被调整以引起列选择信号（CSL）的定时偏移，从而降低读取错误的可能性。特别地，定时控制器响应于第一内部时钟信号（例如，PCLK），并且产生第一和第二控制信号为+ E，ovs CSLE + EE和CSLD。列选择信号发生器响应于第一和第二控制信号。优选地，第一控制信号相对于第一内部时钟信号延迟和反相第一延迟，并且第二控制信号优选地相对于第一内部时钟信号延迟小于第一延迟的第二延迟。定时控制器还通过调整第一和第二延迟的值作为至少一个等待时间状态信号的值的函数来调整列选择信号的前沿和后沿中的至少一个的定时。

8. 发明授权

US08638626B2 Row address control circuit semiconductor memory device including the same and method of controlling row address 失效
标题翻译：行地址控制电路半导体存储装置及其控制方法
公开(公告)号：US08638626B2
公开(公告)日：2014-01-28
申请号：US13237353
申请日：2011-09-20
申请人： Hui-Kap Yang , Woo-Seop Jeong , Chul-Sung Park
发明人： Hui-Kap Yang , Woo-Seop Jeong , Chul-Sung Park
IPC分类号： G11C7/00
CPC分类号： G11C29/20 , G11C2029/1802
摘要： A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.
摘要翻译：包括动态存储单元的半导体存储器件的行地址控制电路包括测试模式设置单元，地址计数器和行地址生成单元。测试模式设置单元被配置为响应于测试命令提供指示是否执行测试操作的测试模式信号; 地址计数器被配置为生成逐渐增加的第一地址; 并且行地址生成单元被配置为基于测试模式信号选择性地选择第一地址和第二地址中的一个作为刷新地址，第二地址被外部提供。

9. 发明授权

US07834350B2 Semiconductor device with test pads and pad connection unit 有权
标题翻译：具有测试焊盘和焊盘连接单元的半导体器件
公开(公告)号：US07834350B2
公开(公告)日：2010-11-16
申请号：US12004401
申请日：2007-12-20
申请人： Woo-Seop Jeong
发明人： Woo-Seop Jeong
IPC分类号： H01L23/58
CPC分类号： G11C29/1201 , G01R31/2884 , G11C29/48 , H01L22/32 , H01L2224/05554 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.
摘要翻译：半导体器件包括至少一种第一类型的焊盘和至少一种第二类型的焊盘，其具有与第一类型焊盘不同的区域。焊盘连接单元在测试模式期间将所述至少一个第二类型的焊盘电耦合到所述半导体器件的集成电路，并且在正常操作模式期间将所述至少一个第二类型的焊盘与所述集成电路断开。

10. 发明授权

US5835444A Method for controlling data output buffer for use in operation at high frequency of synchronous memory 失效
标题翻译：用于控制同步存储器高频操作的数据输出缓冲器的方法
公开(公告)号：US5835444A
公开(公告)日：1998-11-10
申请号：US712346
申请日：1996-09-11
申请人： Gyu-Hong Kim , Woo-Seop Jeong
发明人： Gyu-Hong Kim , Woo-Seop Jeong
IPC分类号： G11C11/409 , G06F13/00 , G11C7/10 , G11C7/22 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/22
摘要： Methods and apparatus for controlling output buffer circuitry in a synchronous semiconductor memory device. An internal clock signal is generated and logic provided to provide a control signal that enables that output buffer circuitry for a read operation. An internal clock signal is generated synchronized to the external or system clock signal. An intermediate control signal is triggered by the internal clock signal at a selected number of cycles less than the memory latency period after a read command, and then the control signal for enabling the output buffer is asserted on a subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer control signal to propagate through the memory device before data is transferred out of the device.
摘要翻译：用于控制同步半导体存储器件中的输出缓冲器电路的方法和装置。产生内部时钟信号，并提供逻辑以提供控制信号，使得该输出缓冲器电路能够进行读取操作。产生与外部或系统时钟信号同步的内部时钟信号。中间控制信号由内部时钟信号以小于读取命令之后的存储器等待时间周期的所选择的周期触发，然后在内部时钟信号的后续周期上断言用于使能输出缓冲器的控制信号，从而在数据被传送出设备之前确保输出缓冲器控制信号至少预定的最小时间传播通过存储器件。

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