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1. 发明授权

US07397283B2 Digital A/V transmission PHY signaling format conversion, multiplexing, and de-multiplexing 有权
标题翻译：数字A / V传输PHY信令格式转换，复用和解复用
公开(公告)号：US07397283B2
公开(公告)日：2008-07-08
申请号：US11537377
申请日：2006-09-29
申请人： Jimmy Chiu , Ming Qu , Ji Zhao
发明人： Jimmy Chiu , Ming Qu , Ji Zhao
IPC分类号： H03K19/094 , H04N7/01
CPC分类号： H04N5/4403 , H04N5/46 , H04N21/43632
摘要： A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal format signal which is received by the multiplexer or demultiplexer. The configurable driver circuit receives the internal format signal from the multiplexer or demultiplexer.
摘要翻译：电路包括可配置接收器电路，耦合到可配置接收器电路的多路复用器或解复用器以及耦合到多路复用器或解复用器的可配置驱动器电路。可配置的接收器电路产生由多路复用器或解复用器接收的内部格式信号。可配置驱动器电路从多路复用器或解复用器接收内部格式信号。

2. 发明申请

US20080079462A1 Digital A/V Transmission PHY Signaling Format Conversion, Multiplexing, and De-Multiplexing 有权
标题翻译：数字A / V传输PHY信令格式转换，复用和解复用
公开(公告)号：US20080079462A1
公开(公告)日：2008-04-03
申请号：US11537377
申请日：2006-09-29
申请人： Jimmy Chiu , Ming Qu , Ji Zhao
发明人： Jimmy Chiu , Ming Qu , Ji Zhao
IPC分类号： H03K19/094
CPC分类号： H04N5/4403 , H04N5/46 , H04N21/43632
摘要： A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal format signal which is received by the multiplexer or demultiplexer. The configurable driver circuit receives the internal format signal from the multiplexer or demultiplexer.
摘要翻译：电路包括可配置接收器电路，耦合到可配置接收器电路的多路复用器或解复用器以及耦合到多路复用器或解复用器的可配置驱动器电路。可配置的接收器电路产生由多路复用器或解复用器接收的内部格式信号。可配置驱动器电路从多路复用器或解复用器接收内部格式信号。

3. 发明授权

US06825733B1 Low jitter integrated phase locked loop with broad tuning range 有权
标题翻译：具有宽调谐范围的低抖动集成锁相环
公开(公告)号：US06825733B1
公开(公告)日：2004-11-30
申请号：US10300190
申请日：2002-11-20
申请人： Ming Qu , Ji Zhao
发明人： Ming Qu , Ji Zhao
IPC分类号： H03B2100
CPC分类号： H03L7/18 , H03L7/095 , H03L7/0995 , H03L7/107 , Y10S331/02
摘要： System and method for providing a low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.
摘要翻译：用于提供具有宽调谐范围（1GHz至10GHz或更大）的低噪声信号的系统和方法，相关抖动不超过目标输出信号的选定周期的约10％。在第一级中，基于环的VCO锁相环系统提供具有一些相关噪声的宽调谐范围，并且第一状态中的第二级相对是透明的，基于频率没有实质的差分衰减。在实现相位锁定之后，基于输入信号频率，第二级被切换到具有低相关噪声和高差分衰减的第二状态。

4. 发明授权

US06492877B1 Coupling for LC-based VCO 有权
标题翻译：用于基于LC的VCO的耦合
公开(公告)号：US06492877B1
公开(公告)日：2002-12-10
申请号：US09927289
申请日：2001-08-09
申请人： Edwin Chan , Ming Qu , Ji Zhao
发明人： Edwin Chan , Ming Qu , Ji Zhao
IPC分类号： H03B518
CPC分类号： H03B27/00 , H03B5/1206 , H03B2200/0078
摘要： A two-stage coupling loop system that provides in-phase and quadrature signals in two stages. Each stage includes a signal coupler, an LC-based voltage controlled oscillator (VCO) and in-loop signal buffer that provides an additional controllable phase shift. Inclusion of the buffers in the loop decreases the capacitance load of each VCO.
摘要翻译：两级耦合回路系统，分两阶段提供同相和正交信号。每个级包括信号耦合器，基于LC的压控振荡器（VCO）和环路信号缓冲器，其提供附加的可控相移。将缓冲器包含在环路中会降低每个VCO的电容负载。

5. 发明授权

US06832231B1 Multiple width random number generation 失效
标题翻译：多宽度随机数生成
公开(公告)号：US06832231B1
公开(公告)日：2004-12-14
申请号：US09966967
申请日：2001-09-28
申请人： Xueping Jiang , Ming Qu , Ji Zhao
发明人： Xueping Jiang , Ming Qu , Ji Zhao
IPC分类号： G06F758
CPC分类号： G06F7/584 , G06F2207/582
摘要： Method and system for generating a multiple width (e.g., 16-bit width) pseudo-random number (PRN). Each of first and second 8-bit width PRNs is generated, using first and second LFSR configurations that incorporate first and second characteristic polynomials, at least one of which is irreducible. The first and second 8-bit PRNs are generated on a rising edge and on a falling edge, respectively, of a clock signal. The first and second 8-bit PRNs are combined by concatenation or by interleaving to form a 16-bit, or other multiple width, PRN.
摘要翻译：用于产生多个宽度（例如，16位宽度）伪随机数（PRN）的方法和系统。使用包含第一和第二特征多项式的第一和第二LFSR配置来生成第一和第二8位宽度PRN中的每一个，其中至少一个是不可约的。第一和第二8位PRN分别在时钟信号的上升沿和下降沿产生。第一和第二8位PRN通过级联或交织来组合以形成16位或其他多宽度的PRN。

6. 发明授权

US06650188B1 Coupling for LC-based VCO 有权
标题翻译：用于基于LC的VCO的耦合
公开(公告)号：US06650188B1
公开(公告)日：2003-11-18
申请号：US10309302
申请日：2002-12-02
申请人： Edwin Chan , Ming Qu , Ji Zhao
发明人： Edwin Chan , Ming Qu , Ji Zhao
IPC分类号： H03B518
CPC分类号： H03B27/00 , H03B5/1206 , H03B2200/0078
摘要： A two-stage coupling loop system that provides in-phase and quadrature signals in the two stages. Each stage includes a signal coupler, an LC-based voltage controlled oscillator (VCO) and an in-loop signal buffer that provides an additional controllable phase shift. Inclusion of the buffers in the loop decreases the capacitance load of each VCO.
摘要翻译：两级耦合回路系统，在两个阶段提供同相和正交信号。每个级包括信号耦合器，基于LC的压控振荡器（VCO）和提供附加可控相移的环路信号缓冲器。将缓冲器包含在环路中会降低每个VCO的电容负载。

7. 发明授权

US06525617B1 Buffering for LC-based stage 失效
标题翻译：缓冲基于LC的舞台
公开(公告)号：US06525617B1
公开(公告)日：2003-02-25
申请号：US09927612
申请日：2001-08-09
申请人： Edwin Chan , Ming Qu , Ji Zhao
发明人： Edwin Chan , Ming Qu , Ji Zhao
IPC分类号： H03B2760
CPC分类号： H03B5/24
摘要： A two-stage ring oscillator system that provides a phase shift of 90° in each of the two stages. Each stage includes an LC-based stage including a voltage controlled oscillator (VCO) and an in-line signal buffer that provides an additional controllable phase shift in the forward path and reduces loading capacitance of each LC-based stage by an estimated 10-50 percent. In-phase and quadrature output signals are provided by the system.
摘要翻译：两级环形振荡器系统，在两个阶段的每个阶段提供90°的相移。每个级包括一个基于LC的级，包括一个压控振荡器（VCO）和一个在线信号缓冲器，在前向通路中提供额外的可控相移，并将每个基于LC的级的负载电容降低10-50 百分。同相和正交输出信号由系统提供

8. 发明授权

US06498538B1 Low jitter integrated phase locked loop with broad tuning range 有权
标题翻译：具有宽调谐范围的低抖动集成锁相环
公开(公告)号：US06498538B1
公开(公告)日：2002-12-24
申请号：US09870877
申请日：2001-05-30
申请人： Ming Qu , Ji Zhao
发明人： Ming Qu , Ji Zhao
IPC分类号： H03L7095
CPC分类号： H03L7/18 , H03L7/095 , H03L7/0995 , H03L7/107 , Y10S331/02
摘要： System and method for providing low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.
摘要翻译：用于提供具有宽调谐范围（1GHz至10GHz或更大）的低噪声信号的系统和方法，相关抖动不超过目标输出信号的选定周期的约10％。在第一级中，基于环的VCO锁相环系统提供具有一些相关噪声的宽调谐范围，并且第一状态中的第二级相对是透明的，基于频率没有实质的差分衰减。在实现相位锁定之后，基于输入信号频率，第二级被切换到具有低相关噪声和高差分衰减的第二状态。

9. 发明申请

US20110150055A1 Active Auxiliary Channel Buffering 有权
标题翻译：主动辅助通道缓冲
公开(公告)号：US20110150055A1
公开(公告)日：2011-06-23
申请号：US12645240
申请日：2009-12-22
申请人： Ming Qu , Zhengyu Yuan , Kochung Lee
发明人： Ming Qu , Zhengyu Yuan , Kochung Lee
IPC分类号： H04B1/38
CPC分类号： G09G5/006 , G09G2330/021 , G09G2350/00 , G09G2370/045 , G09G2370/10 , H04L65/4023 , H04L65/4092 , H04L67/34
摘要： A system and a method for communicating configuration data between a source device and a sink are described. An active buffer receives data from an auxiliary communication channel which communicates data between the source device and the sink device. The active buffer modifies data received from the auxiliary communication channel. For example, the active buffer amplifies the received data or electrically reshapes the received data. The modified data is then transmitted from the active buffer to a destination device. In one embodiment, the auxiliary communication channel is bi-directional and upon receiving data from a first device, the active buffer is modified to permit uni-directional transmission of data from the first device to a second device.
摘要翻译：描述用于在源设备和宿之间传送配置数据的系统和方法。主动缓冲器从辅助通信信道接收数据，该辅助通信信道在源设备和宿设备之间传送数据。主动缓冲器修改从辅助通信信道接收到的数据。例如，有源缓冲器放大所接收的数据或电接收数据。然后将修改的数据从活动缓冲器发送到目的地设备。在一个实施例中，辅助通信信道是双向的，并且在从第一设备接收数据时，主动缓冲器被修改以允许将数据从第一设备单向传输到第二设备。

10. 发明申请

US20140003480A1 On Die Jitter Tolerance Test 有权
标题翻译：关于死机容忍测试
公开(公告)号：US20140003480A1
公开(公告)日：2014-01-02
申请号：US13538930
申请日：2012-06-29
申请人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
发明人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
IPC分类号： H04B17/00
CPC分类号： H03L7/087 , G01R29/26 , H03L7/0807 , H03L7/081 , H03L7/0998 , H04B17/104 , H04L1/205 , H04L1/243 , H04L7/033
摘要： A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.
摘要翻译：公开了一种用于执行裸片抖动容限测试的系统和方法。基于输入信号产生一组时钟。该组时钟包括基于输入信号的数据切换沿的同相信号。此外，该组时钟包括偏移180度的反相时钟相位和一对相位偏移一定数量度θ的时钟。基于反相时钟和两个相移时钟对数据输入进行采样。可以基于反相时钟和两个相移时钟中的每一个是否以各种θ值从输入信号中采样正确的数据来确定输入信号的开眼。

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