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1. 发明申请

US20080026520A1 Semiconductor Method and Device with Mixed Orientation Substrate 有权
标题翻译：具有混合取向基板的半导体方法和器件
公开(公告)号：US20080026520A1
公开(公告)日：2008-01-31
申请号：US11868001
申请日：2007-10-05
申请人： Jiang Yan , Chun-Yung Sung , Danny Shum , Alois Gutmann
发明人： Jiang Yan , Chun-Yung Sung , Danny Shum , Alois Gutmann
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/045 , H01L29/78687
摘要： In a method of forming a semiconductor device, a wafer includes a first semiconductor region of a first crystal orientation and a second semiconductor region of a second crystal orientation. Insulating material is formed over the wafer. A first portion of the insulating material is removed to expose the first semiconductor region and a second portion of the insulating material is removed to expose the second semiconductor region. Semiconductor material of the first crystal orientation is epitaxially grown over the exposed first semiconductor region and semiconductor material of the second crystal orientation is epitaxially grown over the exposed second semiconductor region
摘要翻译：在形成半导体器件的方法中，晶片包括第一晶体取向的第一半导体区域和第二晶体取向的第二半导体区域。在晶片上形成绝缘材料。除去绝缘材料的第一部分以暴露第一半导体区域，并且去除绝缘材料的第二部分以暴露第二半导体区域。在暴露的第一半导体区域上外延生长第一晶体取向的半导体材料，并且在暴露的第二半导体区域上外延生长第二晶体取向的半导体材料

2. 发明申请

US20060170045A1 Semiconductor method and device with mixed orientation substrate 有权
标题翻译：具有混合取向衬底的半导体方法和器件
公开(公告)号：US20060170045A1
公开(公告)日：2006-08-03
申请号：US11047928
申请日：2005-02-01
申请人： Jiang Yan , Chun-Yung Sung , Danny Shum , Alois Gutmann
发明人： Jiang Yan , Chun-Yung Sung , Danny Shum , Alois Gutmann
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/045 , H01L29/78687
摘要： A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.
摘要翻译：半导体器件包括具有第一晶体取向的半导体材料的半导体本体。在第一晶体取向的半导体材料中形成第一晶体管。绝缘层覆盖半导体本体的部分，并且半导体层覆盖绝缘层。半导体层具有第二晶体取向。在具有第二晶体取向的半导体层中形成第二晶体管。在优选实施例中，半导体本体是（100）硅，第一晶体管是NMOS晶体管，半导体层是（110）硅，第二晶体管是PMOS晶体管。

3. 发明申请

US20070057307A1 Embedded flash memory devices on SOI substrates and methods of manufacture thereof 有权
标题翻译： SOI衬底上的嵌入式闪存器件及其制造方法
公开(公告)号：US20070057307A1
公开(公告)日：2007-03-15
申请号：US11223235
申请日：2005-09-09
申请人： Danny Shum , Armin Tilke , Jiang Yan
发明人： Danny Shum , Armin Tilke , Jiang Yan
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

4. 发明申请

US20060014359A1 Formation of active area using semiconductor growth process without STI integration 有权
标题翻译：使用半导体生长过程形成活性区，无需STI整合
公开(公告)号：US20060014359A1
公开(公告)日：2006-01-19
申请号：US10891540
申请日：2004-07-15
申请人： Jiang Yan , Danny Shum
发明人： Jiang Yan , Danny Shum
IPC分类号： H01L21/76
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.
摘要翻译：可以不使用STI工艺来形成半导体器件。在半导体本体上形成绝缘层。绝缘层的一部分被去除以暴露半导体本体，例如露出裸硅。半导体材料，例如硅，生长在暴露的半导体本体上。然后可以在生长的半导体材料中形成诸如晶体管的器件。

5. 发明申请

US20070122985A1 Formation of active area using semiconductor growth process without STI integration 有权
公开(公告)号：US20070122985A1
公开(公告)日：2007-05-31
申请号：US11657825
申请日：2007-01-25
申请人： Jiang Yan , Danny Shum
发明人： Jiang Yan , Danny Shum
IPC分类号： H01L21/336
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.

6. 发明申请

US20070148921A1 Mixed orientation semiconductor device and method 有权
标题翻译：混合取向半导体器件及方法
公开(公告)号：US20070148921A1
公开(公告)日：2007-06-28
申请号：US11317737
申请日：2005-12-23
申请人： Jiang Yan , Danny Shum , Armin Tilke
发明人： Jiang Yan , Danny Shum , Armin Tilke
IPC分类号： H01L21/20 , H01L21/84 , H01L21/44
CPC分类号： H01L27/092 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.
摘要翻译：制造半导体器件的方法从半导体晶片开始，半导体晶片包括覆盖第二半导体层的第一半导体层。在半导体晶片中蚀刻第一沟槽。第一个沟槽填充绝缘材料。在第一沟槽内蚀刻第二沟槽并穿过绝缘材料，使得绝缘材料沿着第一沟槽的侧壁保留。第二沟槽露出第二绝缘层的一部分。然后可以使用第二半导体层作为种子层在第二沟槽内生长半导体层。

7. 发明申请

US20050009290A1 METHOD OF FORMING SHALLOW TRENCH ISOLATION USING DEEP TRENCH ISOLATION 有权
标题翻译：使用深层隔离分离法形成浅层分离的方法
公开(公告)号：US20050009290A1
公开(公告)日：2005-01-13
申请号：US10615630
申请日：2003-07-09
申请人： Jiang Yan , Danny Shum
发明人： Jiang Yan , Danny Shum
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76229
摘要： A method of isolating active areas of a semiconductor workpiece. Deep trenches are formed in a workpiece between adjacent first active areas, and an insulating layer and a semiconductive material are deposited in the deep trenches. The semiconductive material is recessed below a top surface of the workpiece. Shallow trenches are formed in the workpiece between adjacent second active areas, and an insulating material is deposited in the shallow trenches and in the semiconductive material recess. The deep trenches may also be formed between an adjacent first active area and second active area. The first active areas may be high voltage devices, and the second active areas may be low voltage devices. The shallow trench isolation over the recessed semiconductive material in the deep trenches is self-aligned.
摘要翻译：隔离半导体工件的有源区的方法。深沟槽在相邻的第一有源区域之间的工件中形成，并且绝缘层和半导体材料沉积在深沟槽中。半导体材料在工件的顶表面下方凹进。在相邻的第二有源区域之间的工件中形成浅沟槽，并且在浅沟槽和半导体材料凹部中沉积绝缘材料。深沟槽也可以形成在相邻的第一有源区域和第二有源区域之间。第一有源区可以是高压器件，而第二有源区可以是低电压器件。在深沟槽中的凹陷半导体材料上的浅沟槽隔离是自对准的。

8. 发明授权

US08389357B2 Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns 有权
标题翻译：一种具有存储阵列的存储器件的制造方法，所述存储器阵列包括以行和列排列的多个存储单元晶体管
公开(公告)号：US08389357B2
公开(公告)日：2013-03-05
申请号：US13052728
申请日：2011-03-21
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L21/336
CPC分类号： G11C16/0416 , H01L27/115 , H01L29/8616
摘要： A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.
摘要翻译：一种在半导体衬底中制造存储器件的方法，该器件具有存储器阵列，该存储器阵列具有排列成行和列的多个存储单元晶体管。该方法包括形成多个隧穿场效应晶体管，形成第二掺杂类型的第一阱，形成围绕第一阱的第一掺杂类型的第二阱，形成连接到第一行存储单元晶体管的第一字线形成第一位线，以控制第一列存储单元晶体管的隧穿场效应晶体管的掺杂漏极区的电压，以及形成与第一位线平行的第二位线。

9. 发明授权

US07190022B2 One transistor flash memory cell 有权
标题翻译：一个晶体管闪存单元
公开(公告)号：US07190022B2
公开(公告)日：2007-03-13
申请号：US11081886
申请日：2005-03-16
申请人： Danny Shum , Georg Tempel , Ronald Kakoschke
发明人： Danny Shum , Georg Tempel , Ronald Kakoschke
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11546
摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.
摘要翻译：集成电路具有高电压区域，逻辑区域和存储器阵列，用于在包括线性，逻辑和存储器件的芯片上形成系统。存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

10. 发明授权

US07176088B2 Bitline structure and method for production thereof 有权
标题翻译：位线结构及其制造方法
公开(公告)号：US07176088B2
公开(公告)日：2007-02-13
申请号：US10513163
申请日：2004-03-18
申请人： Ronald Kakoschke , Danny Shum , Georg Tempel
发明人： Ronald Kakoschke , Danny Shum , Georg Tempel
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66833
摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.
摘要翻译：本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

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